XR72L52 Datasheet, PDF (356/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-4
Error
Interrupt
Status
RUR
0
BIT 1
Framing
Error
Interrupt
Status
RUR
1
BIT 0
Not Used
RUR
0
Whenever the Terminal Equipment encounters the Detection of Framing Error Interrupt, it should do the follow-
ing.
• It should read the contents of the PMON Framing Bit/Byte Error Count Registers (located at Addresses 0x52
and 0x53) in order to determine the number of Framing errors that have been received by the XRT72L52
Framer IC.
5.3.6.2.9 The Receipt of New LAPD Message Interrupt
If the Receive LAPD Message Interrupt is enabled, then the XRT72L52 Framer IC will generate an interrupt
anytime the Receive HDLC Controller block has received a new LAPD Message frame from the Remote Termi-
nal Equipment, and has stored the contents of this message into the Receive LAPD Message buffer.
Enabling/Disabling the Receive LAPD Message Interrupt
The user can enable or disable the Receive LAPD Message Interrupt by writing the appropriate data into Bit 1
(RxLAPD Interrupt Enable) within the Rx E3 LAPD Control Register, as indicated below.
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
BIT 4
RO
RO
RO
0
0
0
BIT 3
RO
0
BIT 2
RxLAPD
Enable
R/W
0
BIT 1
BIT 0
RxLAPD
RxLAPD
Interrupt Enable Interrupt Enable
R/W
RUR
X
0
Writing a “1” into this bit-field enables the Receive LAPD Message Interrupt. Conversely, writing a “0” into this
bit-field disables the Receive LAPD Message Interrupt.
Servicing the Receive LAPD Message Interrupt
Whenever the XRT72L52 Framer IC generates this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 0 (RxLAPD Interrupt Status), within the Rx E3 LAPD Control register to “1”, as indicated below.
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
RxLAPD
Interrupt Enable Interrupt Status
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
0
1
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