XR72L52 Datasheet, PDF (350/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
1. It should transmit a FERF (Far-End-Receive Failure) indicator to the Remote Terminal Equipment. Please
see Section 5.2.4.2.1.3.
If the OOF state is FALSE
1. It should cease transmitting the FERF indication to the Remote Terminal Equipment.
NOTE: The device cannot be configured to automatically send/clear FERF on LOS, LOOf, OOF or AIS in E3 G.751 mode.
The user must implemt it in the ISR.
Please see Section 5.2.4.2.1.3 on how to control the state of the A bit, which is transmitted via each outbound
E3 frame.
5.3.6.2.3 The Change in Receive LOF Condition Interrupt
If the Change in Receive LOF Condition Interrupt is enabled, then the XRT72L52 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L52 Framer IC declares an LOF (Out of Frame) Condition, and
2. When the XRT72L52 Framer IC clears the LOF condition.
Conditions causing the XRT72L52 Framer IC to declare an LOF Condition.
• If the Receive E3 Framer block (within the XRT72L52 Framer IC) detects Framing Bit errors, within four con-
secutive incoming E3 frames, and is not capable of transition back into the In-Frame state within a 1ms or
3ms period.
Conditions causing the XRT72L52 Framer IC to clear the LOF Condition.
• If the Receive E3 Framer block transitions from the OOF Condition state to the LOF Condition state (see
Figure 124).
• If the Receive E3 Framer block transitions back into the In-Frame state.
Enabling and Disabling the Change in Receive LOF Condition Interrupt
The user can enable or disable the Change in Receive LOF Condition Interrupt, by writing the appropriate val-
ue into Bit 2 (LOF Interrupt Enable), within the RxE3 Interrupt Enable Register - 1, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
X
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change in Receive LOF Condition Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 6 (LOF Interrupt Status), within the Rx E3 Interrupt Status Register - 1 to “1”, as indicated below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
0
0
1
1
1
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