XR72L52 Datasheet, PDF (188/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
For DS3 applications, the Transmit DS3 Framer block automatically generates and inserts the framing align-
ment bits (e.g., the F and M bits) into the outbound DS3 frames. Further, the Transmit DS3 Framer block will
automatically compute and insert the P-bits into the outbound DS3 frames. Hence, the Transmit DS3 Framer
block will not accept data from the Transmit OH Data Input Interface block for the F, M and P bits.
However, the Transmit DS3 Framer block will accept (and insert) data from the Transmit Overhead Data Input
Interface for the following bit-fields.
• X-bits
• FEBE bits
• FEAC bits
• DL bits
• UDL bits
• CP bits
If the user's local Data Link Equipment activates the Transmit Overhead Data Input Interface block and writes
data into this interface for these bits, then the Transmit DS3 Framer block will insert this data into the appropri-
ate overhead bit-fields, within the outbound DS3 frames.
Handling of Data from the Transmit HDLC Controller block
The exact manner in how the Transmit DS3 Framer handles data from the Transmit HDLC Controller block de-
pends upon whether the Transmit HDLC Controller is transmitting BOS (Bit Oriented Signaling) or MOS (Mes-
sage Oriented Signaling) data.
If the Transmit DS3 HDLC Controller block is not activated, then the Transmit DS3 Framer block will insert a “1”
into each FEAC and DL bit-field, within each outbound DS3 frame.
If the Transmit DS3 HDLC Controller block is activated, and is configured to transmit either a BOS or MOS type
message, then data will be inserted into the FEAC and DL bit-fields as described in Section 4.2.3.
4.2.4.2 Detailed Functional Description of the Transmit DS3 Framer Block
The Transmit DS3 Framer receives data from the following three sources and combines them together to form
a DS3 data stream.
• The Transmit Payload Data Input Interface block.
• The Transmit Overhead Data Input Interface block
• The Transmit HDLC Controller block.
Afterwards, this DS3 data stream will be routed to the Transmit DS3 LIU Interface block, for further processing.
Figure 52 presents a simple illustration of the Transmit DS3 Framer block, along with the associated paths to
the other functional blocks within the chip.
172