XR72L52 Datasheet, PDF (225/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Flag Sequence Byte detected
Abort Sequence detected
Message Type
C/R Type
The occurrence of FCS Errors
The LAPD receiver's actions are facilitated via the following two registers.
• Rx DS3 LAPD Control Register
• Rx DS3 LAPD Status Register
Operation of the LAPD Receiver
The LAPD Receiver, once enabled, will begin searching for the boundaries of the incoming LAPD message.
The LAPD Message Frame boundaries are delineated via the Flag Sequence octets (0x7E), as depicted in
Figure 73.
FIGURE 73. LAPD MESSAGE FRAME FORMAT
Flag Sequence (8 bits)
SAPI (6-bits)
TEI (7 bits)
Control (8-bits)
C/R EA
EA
76 or 82 Bytes of Information (Payload)
FCS - MSB
FCS - LSB
Flag Sequence (8-bits)
Where: Flag Sequence = 0x7E
SAPI + CR + EA = 0x3C or 0x3E
TEI + EA = 0x01
Control = 0x03
The 16 bit FCS is calculated using CRC-16, x16 + x12 + x5 + 1
The first byte of the information field indicates the type and size of the message being transferred. The value
of this information or payload field and the corresponding message type/size follow:
CL Path Identification = 0x38 (76 bytes)
IDLE Signal Identification = 0x34 (76 bytes)
Test Signal Identification = 0x32 (76 bytes)
ITU-T Path Identification = 0x3F (82 bytes)
The LAPD Receiver must be enabled before it can begin receiving any LAPD messages. The LAPD Receiver
can be enabled by writing a "1" into Bit 2 (RxLAPD Enable) within the Rx DS3 LAPD Control Register. The bit
format of this register is depicted below.
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