XR72L52 Datasheet, PDF (123/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Bits 3 - 0: TxBIP-4 Mask[3:0]
This Read/Write bit-field permits the user to insert errors into the BIP-4 value within each outbound E3 frame.
The user may wish to do this for equipment testing purposes. Prior to transmission, the Transmit DS3/E3
Framer block reads in the BIP-4 value, and performs an XOR operation with it and the contents of this register.
The results of this operation are written back into the BIP-4 nibble position, in each outbound E3 frame. Con-
sequently, to insure errors are not injected into the BIP-4 value of the outbound E3 frames, the contents of this
register must be set to all "0’s" (the default value).
NOTE: This register is ignored if Bit 7 (Tx BIP-4 Enable) within the TxE3 Configuration register (Address = 0x30) is set to
“0”.
2.3.8 Performance Monitor Registers
2.3.8.1 PMON Line Code Violation Count Register - MSB
PMON LCV EVENT COUNT REGISTER - MSB (ADDRESS = 0X50)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x51) con-
tains a 16-bit representation of the number of Line Code Violations that have been detected by the Receive
DS3/E3 Framer block, since the last read of these registers. This register contains the MSB (or Upper-Byte)
value of this 16 bit expression.
2.3.8.2 PMON Line Code Violation Count Register - LSB
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x50) con-
tains a 16-bit representation of the number of Line Code Violations that have been detected by the Receive
DS3/E3 Framer block, since the last read of these registers. This register contains the LSB (or Lower-Byte)
value of this 16 bit expression.
2.3.8.3 PMON Framing Bit/Byte Error Count Register - MSB
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framing Bit/Byte Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON Framing Bit/Byte Error Count Register - LSB (Address =
0x53) contains a 16-bit representation of the number of Framing Bit or Byte Errors that have been detected by
the Receive DS3/E3 Framer block, since the last read of these registers. This register contains the MSB (or
Upper-Byte) value of this 16 bit expression.
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