XR72L52 Datasheet, PDF (10/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12).......................................................................231
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13).......................................................................231
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ...........................................................232
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12).......................................................................232
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13).......................................................................233
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ...........................................................233
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12).......................................................................234
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13).......................................................................234
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ........................................................................................234
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12).......................................................................235
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13).......................................................................235
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12).......................................................................236
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13).......................................................................236
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12).......................................................................237
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13).......................................................................237
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ...............................................238
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ...............................................238
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ...............................................239
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ...............................................239
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ...........................................................................240
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ...........................................................................240
5.0 E3/ITU-T G.751 Operation of the XRT72L52 ....................................................................................241
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................241
5.1 DESCRIPTION OF THE E3, ITU-T G.751 FRAMES AND ASSOCIATED OVERHEAD BITS ......................................... 241
Figure 85. Illustration of the E3, ITU-T G.751 Framing Format..................................................................................... 241
5.1.1 Definition of the Overhead Bits............................................................................................................. 241
5.2 THE TRANSMIT SECTION OF THE XRT72L52 (E3, ITU-T G.751 MODE OPERATION) .......................................... 242
Figure 86. The XRT72L52 Transmit Section configured to operate in the E3 Mode .................................................... 243
5.2.1 The Transmit Payload Data Input Interface Block ................................................................................ 243
Figure 87. The Transmit Payload Data Input Interface Block ....................................................................................... 243
TABLE 43: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE .... 244
Figure 88. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 1 (Serial/
Loop-Timed) Operation.................................................................................................................................. 246
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ..............................................................................247
Figure 89. Behavior of the Terminal Interface signals between the XRT72L52 Transmit Payload Data Input Interface block
and the Terminal Equipment (for Mode 1 Operation) .................................................................................... 248
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................248
Figure 90. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 2 (Serial/
Local-Timed/Frame-Slave) Operation ........................................................................................................... 249
Figure 91. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (Mode 2
Operation)...................................................................................................................................................... 250
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................251
Figure 92. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 3 (Serial/
Local-Timed/Frame-Master) Operation ......................................................................................................... 252
Figure 93. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (E3 Mode 3
Operation)...................................................................................................................................................... 253
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................253
Figure 94. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 4 (Nibble-
Parallel/Loop-Timed) Operation..................................................................................................................... 254
Figure 95. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (Mode 4
Operation)...................................................................................................................................................... 255
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................255
Figure 96. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 5 (Nibble-
Parallel/Local-Timed/Frame-Slave) Operation .............................................................................................. 257
Figure 97. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (E3, Mode 5
Operation)...................................................................................................................................................... 258
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................258
Figure 98. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 6 (Nibble-
Parallel/Local-Timed/Frame-Master) Operation ............................................................................................ 259
Figure 99. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (E3 Mode 6
VIII