XR72L52 Datasheet, PDF (125/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
This Reset-upon-Read register, along with the PMON FEBE Event Count Register - LSB (Address = 0x57)
contains a 16-bit representation of the number of FEBE Events that have been detected by the Receive DS3/
E3 Framer block, since the last read of these registers. This register contains the MSB (or Upper-Byte) value
of this 16 bit expression.
2.3.8.8 PMON FEBE Event Count Register - LSB
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FEBE Event Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON FEBE Event Count Register - MSB (Address = 0x56)
contains a 16-bit representation of the number of FEBE Events that have been detected by the Receive DS3/
E3 Framer block, since the last read of these registers. This register contains the LSB (or Lower-Byte) value of
this 16 bit expression.
2.3.8.9 PMON CP-Bit Error Event Count Register - MSB
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON CP-Bit Error Count Register - LSB (Address = 0x59)
contains a 16-bit representation of the number of CP-bit Errors that have been detected by the Receive DS3/
E3 Framer block (within the channel), since the last read of these registers. This register contains the MSB (or
Upper-Byte) value of this 16 bit expression.
NOTE: This register is only active if the Channel has been configured to operate in the DS3, C-bit Parity Framing format.
2.3.8.10 PMON CP-Bit Error Event Count Register - LSB
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON CP-Bit Error Count Register - MSB (Address = 0x58)
contains a 16-bit representation of the number of CP-bit Errors that have been detected by the Receive DS3/
E3 Framer block (within the channel), since the last read of these registers. This register contains the LSB (or
Lower-Byte) value of this 16 bit expression.
NOTE: This register is only active if the Channel has been configured to operate in the DS3, C-bit Parity Framing format.
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