XR72L52 Datasheet, PDF (298/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
Terminal Equipment testing. The user can exercise this option by writing data into any of the following regis-
ters.
• TxE3 FAS Error Mask Register - 0
• TxE3 FAS Error Mask Register - 1
• TxE3 BIP-4 Error Mask Register
Inserting Errors into the FAS pattern of the outbound’ E3 frames.
The user can insert errors into the FAS pattern bits, of each outbound E3 frame, by writing the appropriate data
into either the TxE3 FAS Error Mask Register - 0 or TxE3 FAS Error Mask Register - 1.
As the Transmit E3 Framer block formulates the outbound E3 frames, the contents of the FAS pattern bits are
automatically XORed with the contents of these two registers. The results of this XOR operation is written
back into the corresponding bit-field within the outbound E3 frame, and is transmitted to the Remote Terminal
Equipment. Therefore, if the user does not wish to modify any of these bits, then these registers must contain
all “0’s” (the default value).
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Not Used
TxFAS_Error_Mask_Upper[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
0
0
0
X
X
X
X
BIT 0
R/W
X
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
R/W
X
BIT 3
BIT 2
BIT 1
TxFAS_Error_Mask_Lower[4:0]
R/W
R/W
R/W
X
X
X
BIT 0
R/W
X
Inserting Errors into the BIP-4 nibble, within each outbound E3 frame.
The user can insert errors into the BIP-4 nibble, within each outbound E3 frame, by writing the appropriate data
into the TxE3 BIP-4 Error Mask Register.
As the Transmit E3 Framer block formulates the outbound E3 frames, the contents of the BIP-4 bits are auto-
matically XORed with the contents of this register. The results of this XOR operation is written back into the
corresponding bit-field within the outbound E3 frame, and is transmitted to the Remote Terminal Equipment.
Therefore, if the user does not wish to modify any of these bits, then this register must contain all “0’s” (the de-
fault value).
NOTE: This register is only active if the XRT72L52 Framer IC has been configured to insert the BIP-4 nibble into each out-
bound E3 frame.
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
R/W
0
BIT 6
BIT 5
Not Used
R/W
R/W
0
0
BIT 4
R/W
0
BIT 3
R/W
0
BIT 2
BIT 1
TxBIP-4 Mask[3:0]
R/W
R/W
0
0
BIT 0
R/W
0
5.2.5 The Transmit E3 Line Interface Block
282