XR72L52 Datasheet, PDF (405/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
This read/write bit field allows the user to transmit an LOS (Loss of Signal) pattern to the remote terminal, upon
software control. Table 76 relates the contents of this bit field to the Transmit E3 Framer block's action.
TABLE 76: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION
BIT 1
0
1
TRANSMIT E3 FRAMER'S ACTION
Normal Operation:
The Overhead bits are either internally generated, or they are inserted via the Transmit Overhead Data Input
Interface or the Transmit HDLC Controller blocks. The Payload bits are received from the Transmit Payload
Data Input Interface.
Transmit LOS Pattern:
When this command is invoked the Transmit E3 Framer will do the following.
• Set all of the overhead bytes to "0" (including the FA1 and FA2 bytes)
Overwrite the E3 payload bits with an "all zeros" pattern.
NOTE: When this bit is set, it overrides all of the other bits in this register.
6.2.4.2.1.3 Transmitting FEBE (Far-End Block Error) and FERF (Far-End Receive Failures) indicators
via Software control
The "TxE3 Configuration" register (Address = 0x30) contains a register bit (Bit 0 - TxMARx) that permits the us-
er to control the state of the FEBE and FERF bit-fields, in the outbound E3 data stream.
The bit-format of the "TxE3 Configuration" register is presented below.
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
TxDL in NR
R/W
0
BIT 3
Not Used
BIT 2
TxAIS Enable
RO
R/W
0
0
BIT 1
TxLOS
Enable
R/W
0
BIT 0
TxMARx
R/W
0
This read/write bit-field permits the user to configure the XRT72L52 device to do one of the following.
A. Set the "FEBE" and "FERF" bit-fields (within the MA byte of "outbound" E3 frames) to the appropriate state
based upon conditions detected by the "Receive DS3/E3 Framer" block.
B. To (via software-control) set the states of the "FEBE" and "FERF" bit-fields (within the MA byte of "out-
bound" E3 frames).
Setting this bit-field to "1" configures the Transmit DS3/E3 Framer block to automatically set the FEBE and
FERF bit-fields (within the outbound E3 data stream) to states based upon conditions detected by the Receive
DS3/E3 Framer block.
NOTE: In this mode, the Transmit DS3/E3 Framer block will set and clear the FERF and FEBE bit-fields in response to the
following conditions.
A. FERF bit-field
If the Receive DS3/E3 Framer block (in the same channel) is currently experiencing an LOS, AIS or LOF con-
dition, then the Transmit DS3/E3 Framer block will automatically set the FERF bit-field (in the outbound E3
frame) to "1". Conversely, if the Receive DS3/E3 Framer block is not experiencing any of these conditions,
then the Transmit DS3/E3 Framer block will set the FERF bit-field (in the outbound E3 frame) to "0".
B. FEBE bit-field
If the Receive DS3/E3 Framer block detects a BIP-8 error in the incoming E3 frame, then the Transmit DS3/E3
Framer block will automatically set the FEBE bit-field (in the outbound E3 frame) to "1". Conversely, if the Re-
ceive DS3/E3 Framer block does not detect a BIP-8 error in the incoming E3 frame, then the Transmit DS3/E3
Framer block will set the FEBE bit-field (in the outbound E3 frame) to "0".
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