XR72L52 Datasheet, PDF (336/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
Table 61 relates the number of rising clock edges (in the RxOHClk signal, since the RxOHFrame signal was
last sampled "High”) to the E3 Overhead bit that is being output via the RxOH output pin.
TABLE 61: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE
RXOHFRAME WAS LAST SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH
OUTPUT PIN
NUMBER OF RISING CLOCK EDGES IN RXOHCLK
0 (Clock edge is coincident with RxOHFrame being detected "High”)
1
2
3
4
5
6
7
8
9
10
11
THE OVERHEAD BIT BEING OUTPUT BY THE
XRT72L52
FAS Pattern - Bit 9
FAS Pattern - Bit 8
FAS Pattern - Bit 7
FAS Pattern - Bit 6
FAS Pattern - Bit 5
FAS Pattern - Bit 4
FAS Pattern - Bit 3
FAS Pattern - Bit 2
FAS Pattern - Bit 1
FAS Pattern - Bit 0
A Bit
N Bit
Figure 134 presents the typical behavior of the Receive Overhead Data Output Interface block, when Method 1
is being used to sample the incoming E3 overhead bits.
FIGURE 134. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD OUTPUT INTERFACE
(FOR METHOD 1).
RxOHClk
RxOHFrame
RxOH
FAS, Bit 9
FAS, Bit 8
FAS, Bit 7
FAS, Bit 6
FAS, Bit 5
Terminal Equipment should sample
the “RxOHFrame” and “RxOH” signals
here.
Recommended Sampling Edges
320