XR72L52 Datasheet, PDF (366/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 145. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 1(SERIAL/LOOP-TIMED) OPERATION
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz
RxOutClk
TxSer
TxFrame
TxOH_Ind
NibIntf
Terminal Equipment
E3 Framer
Mode 1 Operation of the Terminal Equipment
When the XRT72L52 is operating in this mode it will function as the source of the 34.368MHz clock signal.
This clock signal will be used as the Terminal Equipment Interface clock by both the XRT72L52 IC and the Ter-
minal Equipment.
The Terminal Equipment will serially output the payload data of the Outbound E3 data stream via its
E3_Data_Out pin. The Terminal Equipment will update the data on the E3_Data_Out pin upon the rising edge
of the 34.368 MHz clock signal, at its E3_Clock_In input pin (as depicted in Figure 145 and Figure 146).
The XRT72L52 will latch the Outbound E3 data stream (from the Terminal Equipment) on the rising edge of the
RxOutClk signal.
The XRT72L52 will indicate that it is processing the last bit, within a given Outbound E3 frame, by pulsing its
TxFrame output pin "High" for one bit-period. When the Terminal Equipment detects this pulse at its
Tx_Start_of_Frame input, it is expected to begin transmission of the very next Outbound E3 frame to the
XRT72L52 via the E3_Data_Out (or TxSer pin).
Finally, the XRT72L52 will indicate that it is about to process an overhead bit by pulsing the TxOH_Ind output
pin "High" one bit period prior to its processing of an OH (Overhead) bit. In Figure 145, the TxOH_Ind output
pin is connected to the E3_Overhead_Ind input pin, of the Terminal Equipment. Whenever the
E3_Overhead_Ind pin is pulsed "High" the Terminal Equipment is expected to not transmit a E3 payload bit up-
on the very next clock edge. Instead, the Terminal Equipment is expected to delay its transmission of the very
next payload bit, by one clock cycle.
The behavior of the signals, between the XRT72L52 and the Terminal Equipment, for E3 Mode 1 operation is il-
lustrated in Figure 146.
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