XR72L52 Datasheet, PDF (7/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Operation)...................................................................................................................................................... 142
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 142
Figure 38. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 4 (Nibble-
Parallel/Loop-Timed) Operation .................................................................................................................... 143
Figure 39. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (Mode 4
Operation)...................................................................................................................................................... 144
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 145
Figure 40. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 5 (Nibble-
Parallel/Local-Timed/Frame-Slave) Operation .............................................................................................. 146
Figure 41. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (DS3 Mode 5
Operation)...................................................................................................................................................... 147
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 147
Figure 42. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 6 (Nibble-
Parallel/Local-Timed/Frame-Master) Operation ............................................................................................ 148
Figure 43. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment (DS3 Mode 6
Operation)...................................................................................................................................................... 149
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 150
4.2.2 The Transmit Overhead Data Input Interface....................................................................................... 151
Figure 44. The Transmit Overhead Data Input Interface block ..................................................................................... 151
TABLE 16: OVERHEAD BITS WITHIN THE DS3 FRAME AND THEIR POTENTIAL SOURCES WITHIN THE XRT72L52 IC ............... 152
TABLE 17: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................ 153
Figure 45. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 1)....... 154
TABLE 18: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK SINCE TXOHFRAME WAS LAST
SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS BEING PROCESSED ......................................................... 154
Figure 46. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L52, in order to configure
the XRT72L52 to transmit a Yellow Alarm to the remote terminal equipment ............................................... 157
TABLE 19: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................ 158
Figure 47. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 2)....... 159
TABLE 20: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES SINCE THE LAST OCCURRENCE OF THE
TXOHFRAME PULSE, TO THE DS3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE XRT72L52..................... 159
Figure 48. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L52 and the Terminal Equipment
(for Method 2) ................................................................................................................................................ 162
4.2.3 The Transmit DS3 HDLC Controller..................................................................................................... 162
TX DS3 FEAC REGISTER (ADDRESS = 0X32) ......................................................................................... 164
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)................................. 164
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)................................. 164
Figure 49. A Flow Chart depicting how to transmit a FEAC Message via the FEAC Transmitter................................. 165
Figure 50. LAPD Message Frame Format.................................................................................................................... 166
TABLE 21: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE WITHIN THE INFORMATION PAYLOAD
167
TRANSMIT DS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ..................................................... 167
TABLE 22: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ............................................. 167
TRANSMIT DS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ..................................................... 168
TABLE 23: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ............................................. 168
TRANSMIT DS3 LAPD STATUS/INTERRUPT REGISTER (ADDRESS = 0X34) ................................................ 168
Figure 51. Flow Chart depict how to use the LAPD Transmitter ................................................................................... 170
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 171
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ....................................................................... 171
4.2.4 The Transmit DS3 Framer Block.......................................................................................................... 171
Figure 52. The Transmit DS3 Framer Block and the associated paths to other Functional Blocks .............................. 173
TX DS3 CONFIGURATION REGISTER (ADDRESS = 0X30) .......................................................................... 173
TABLE 24: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 7 (TX YELLOW ALARM) WITHIN THE TX DS3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION........................................................ 174
TABLE 25: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 6 (TX X-BITS) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND
THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION................................................................................ 174
TABLE 26: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 5 (TX IDLE) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND
THE RESULTING TRANSMIT DS3 FRAMER ACTION.............................................................................................. 175
TABLE 27: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 4 (TX AIS PATTERN) WITHIN THE TX DS3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION........................................................ 175
TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND
THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION................................................................................ 176
TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35 ................................................................................. 177
TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36 ................................................................................ 177
V