XR72L52 Datasheet, PDF (41/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
t₂₆ TXOHIns to TxInClk (rising edge) set-up Time
254
XRT72L52
REV. 1.0.1
MAX.
UNITS
CONDITIONS
ns DS3 Applications
72
ns E3, ITU-T G.832
Applications
15
t₂₇ TxInClk clock (rising edge) to TxOHIns hold-time
0
0
ns ^{E3, ITU-T G.751}
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
0
t₂₈ TXOH to TxInClk (rising edge) set-up Time
254
72
ns ^{E3, ITU-T G.751}
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
15
t₂₉ TxInClk clock (rising edge) to TxOH hold-time
0
0
ns ^{E3, ITU-T G.751}
Applications
ns DS3 Applications
ns E3, ITU-T G.832
Applications
0
t_29A TxOHEnable to TxOHIns/TxOH Delay
1
Transmit LIU Interface Timing (see Figure 9 and Figure 10)
t₃₁ Rising or falling edge of TxLineClk to rising edge of
TxPOS or TxNEG
t₃₂ Period of TxLineClk
Receive LIU Interface Timing (see Figure 11 and Figure 12)
t₃₈ RxPOS or RxNEG set-up time to rising edge or fall-
0
ing edge of RxLineClk.
t₃₉ RxPOS or RxNEG hold time, from rising edge or fall- 4
ing edge of RxLineClk
(Framer is configured to sample data on RxPOS and
RxNEG input pins on the rising edge of RxLineClk)
2.4
22.36
29.10
ns ^{E3, ITU-T G.751}
Applications
ns
ns
ns DS3 Applications
ns E3 Applications
ns
ns
25