XR72L52 Datasheet, PDF (73/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.3.2.10 Receive DS3 Interrupt Enable Register
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
AIC
Interrupt
Enable
R/W
0
XRT72L52
REV. 1.0.1
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Bit 7 - CP Bit Error Interrupt Enable
This Read/Write bit-field is used to enable or disable the Detection of CP-Bit Error Interrupt. Setting this bit-
field to “1’ enables this interrupt. Setting this bit-field to “0” disables this interrupt.
NOTES:
1. For more information on the CP-Bit Error Checking/Detection, refer to Section 4.3.2.6.2.
2. This bit-field is only valid if the Channel has been configured to operate in the DS3, C-Bit Parity Framing format.
Bit 6 - LOS Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in LOS condition interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, refer to Section 4.3.2.5.1.
Bit 5 - AIS Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in AIS condition interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, refer to Section 4.3.2.5.2.
Bit 4 - Idle Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in Idle condition interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the Idle Condition, refer to Section 4.3.2.5.3.
Bit 3 - FERF Interrupt Enable
This Read/Write bit-field is used to enable or disable the Change in FERF (Far End Receive Failure) Status in-
terrupt. Setting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on Far-End Receive Failures (or Yellow Alarms), refer to Section 4.3.2.5.4.
Bit 2 - AIC Interrupt Enable
This Read/Write bit field allows the user to enable or disable the Change in AIC value interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on this interrupt condition, refer to Section 4.3.2.5.6.
Bit 1 - OOF Interrupt Enable
This Read/Write bit field is used to enable or disable the Change in Out-of-Frame (OOF) status interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF Condition, refer to Section 4.3.2.2.
Bit 0 - P-Bit Error Interrupt Enable
This Read/Write bit-field is used to enable or disable the Detection of P-Bit Error interrupt. Setting this bit-field
to "1" enables this interrupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on the P-Bit Error Checking/Detection, refer to Section 4.3.2.6.1.
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