XR72L52 Datasheet, PDF (200/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 59. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t₃₂
TxLineClk
t₃₁
t₃₃
TxPOS
TxNEG
4.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT72L52 can generate an interrupt to the Microcontroller/Microprocessor for the
following two reasons.
• Completion of Transmission of FEAC Message
• Completion of Transmission of LAPD Message
4.2.6.1 Enabling Transmit Section Interrupts
The Interrupt Structure, within the XRT72L52 contains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The Enable State of the Block Level for the Transmit Section Interrupts dictates whether or not interrupts (if en-
abled at the source level), are actually enabled.
These Transmit Section interrupts can be enabled or disabled at the Block Level, by writing the appropriate da-
ta into Bit 1 (Tx DS3/E3 Interrupt Enable) within the Block Interrupt Enable register (Address = 0x04), as illus-
trated below.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
0
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Transmit Section (at the Block Level) for Interrupt Generation. Con-
versely, setting this bit-field to “0” disables the Transmit Section for interrupt generation.
What does it mean for the Transmit Section Interrupts to be enabled or disabled at the Block Level?
If the Transmit Section is disabled (for interrupt generation) at the Block Level, then ALL Transmit Section inter-
rupts are disabled, independent of the interrupt enable/disable state of the source level interrupts.
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