XR72L52 Datasheet, PDF (349/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
• If the Receive E3 Framer block (within the XRT72L52 Framer IC) transitions from the FAS Pattern Verifica-
tion state to the In-Frame state (see Figure 124).
• If the Receive E3 Framer block transitions from the OOF Condition state to the In-Frame state (see
Figure 124).
Enabling and Disabling the Change in Receive OOF Condition Interrupt
The user can enable or disable the Change in Receive OOF Condition Interrupt, by writing the appropriate val-
ue into Bit 3 (OOF Interrupt Enable), within the RxE3 Interrupt Enable Register - 1, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Enable
OOF
Interrupt
Enable
LOF
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
X
0
X
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change in Receive OOF Condition Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 3 (OOF Interrupt Status), within the Rx E3 Interrupt Status Register - 1 to “1”, as indicated below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
RO
RO
RO
RUR
RUR
RUR
RUR
RUR
0
0
0
0
1
0
0
0
Whenever the user’s system encounters the Change in Receive OOF Condition Interrupt, then it should do the
following.
1. It should determine the current state of the OOF condition. Recall, that this interrupt can be generated,
whenever the XRT72L52 Framer IC declares or clears the OOF defect. Hence, the user can determine the
current state of the OOF defect by reading the state of Bit 5 (RxOOF) within the Rx E3 Configuration and
Status Register - 2, as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF Algo RxLOF
RxOOF
RxLOS
RxAIS
RxPld Unstab
Rx
TMark
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
X
X
X
X
X
X
X
X
If the OOF state is TRUE
333