XR72L52 Datasheet, PDF (466/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
1
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error Interrupt
Status
RUR
0
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
• It will write the contents of this newly received Trail Trace Buffer Message, into the RxTTB-0 (located at
0x1C) through RxTTB-15 (located at 0x2B) registers.
Whenever the Terminal Equipment encounters the Change in Trail Trace Buffer Message Interrupt, then it
should read out the contents of the 16 RxTTB registers.
6.3.6.2.7 The Change in Receive FERF Condition Interrupt
If the Change in Receive FERF Condition Interrupt is enabled, then the XRT72L52 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L52 Framer IC declares a FERF (Far-End Receive Failure) Condition, and
2. When the XRT72L52 Framer IC clears the FERF condition.
Conditions causing the XRT72L52 Framer IC to declare an FERF Condition.
• If the XRT72L52 Framer IC begins receiving E3 frames which have the FERF bit (within the MA byte, set to
“1”).
Conditions causing the XRT72L52 Framer IC to clear the FERF Condition.
• If the XRT72L52 Framer IC begins receiving E3 frames that do NOT have the FERF bit set to “1”.
Enabling and Disabling the Change in Receive FERF Condition Interrupt
The user can enable or disable the Change in Receive FERF Condition Interrupt, by writing the appropriate
value into Bit 3 (FERF Interrupt Enable), within the RxE3 Interrupt Enable Register - 2, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change in Receive FERF Condition Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 3 (FERF Interrupt Status), within the Rx E3 Interrupt Status Register - 2 to “1”, as indicated
below
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