XR72L52 Datasheet, PDF (16/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
SAMPLING EDGE OF THE RXLINECLK SIGNAL ..................................................................................................... 403
Figure 179. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the rising edge of RxLineClk ...................................................................................................... 404
Figure 180. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the falling edge of RxLineClk ..................................................................................................... 404
6.3.2 The Receive E3 Framer Block.............................................................................................................. 404
Figure 181. The Receive E3 Framer Block and the Associated Paths to Other Functional Blocks.............................. 405
Figure 182. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Algorithm .. 406
Figure 183. Illustration of the E3, ITU-T G.832 Framing Format................................................................................... 407
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................408
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................408
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................409
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................409
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................409
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) .....................................410
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) ......................................410
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................410
TABLE 82: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE
OF THE RECEIVE E3 FRAMER BLOCK .................................................................................................................411
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................411
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................411
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................412
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................412
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................412
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................413
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................413
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT..........................................................................413
RXE3 CONFIGURATION & STATUS REGISTER 1 - (E3, ITU-T G.832) (ADDRESS = 0X10)...........................414
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X13) ....................................................................414
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................414
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)...........................................................415
Figure 184. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with a
correct EM Byte. ............................................................................................................................................ 415
Figure 185. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
FEBE bit (within the MA byte-field) set to “0”................................................................................................. 416
Figure 186. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with an
incorrect EM Byte. ......................................................................................................................................... 417
Figure 187. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
FEBE bit (within the MA byte-field) set to “1”................................................................................................. 417
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ....................................................................418
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) .......................................................418
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ........................................................418
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ....................................................................419
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56)..........................................................419
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57)...........................................................419
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ....................................................................420
6.3.3 The Receive HDLC Controller Block .................................................................................................... 420
Figure 188. LAPD Message Frame Format .................................................................................................................. 421
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)..............................................................................422
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)..............................................................................422
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................422
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................423
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................423
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................424
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................424
TABLE 83: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MESSAGE TYPE/SIZE
425
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)..............................................................................425
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................425
XIV