XR72L52 Datasheet, PDF (442/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 189. FLOW CHART DEPICTING THE FUNCTIONALITY OF THE LAPD RECEIVER
START
Enable the LAPD Receiver
This is done by writing the value 0xFC into
the RxLAPD Control Register (Adress =
0x18)
LAPD Receiver begins reading in theNR or
GC byte field from each inbound E3 fram e.
Does
LAPD Receiver
detect
6 Consecutive
"Ones"?
Destuff "Zeros"
NO
after any 5
Consecutive
"Ones"
YES
Receive LAPD
Message
1
1
W rite
0x7E
to
0xDE
First Flag
Sequence is
Received
NO
Has first
Flag Sequence
been received?
NO
YES
YES
ABORT
Does
LAPD Receiver
detect
7 Consecutive
"Ones"?
Does
LAPD Receiver
detect
6 Consecutive
"Ones"?
Resart
search for
First Flag
Sequence
YES
1
Does
LAPD Receiver
detect
7 Consecutive
"Ones"?
YES
1
Execute LAPD
Received
Interrupt
Service
Routine
FCS error
bit "High"
NO
Is FCS
verifiy
OK?
YES
Generate
LAPD
Receiver
interrupt
1
NO
End of Message
Write Received
LAPD Message
to Message Buffer
(0xDF thru 0x135)
Compute &
Verify FCS
based on
message length
by message type
6.3.4 The Receive Overhead Data Output Interface
Figure 190 presents a simple illustration of the Receive Overhead Data Output Interface block within the
XRT72L52.
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