XR72L52 Datasheet, PDF (26/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
PIN DESCRIPTION
PIN #
87
PIN NAME
NibbleIntf
88
Reset
89
MOTO
90
CS
91
WR_R/W
92
ALE_AS
93
NC
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TYPE
DESCRIPTION
I Nibble Interface Select Input Pin:
This input pin allows the user to configure the Transmit Payload Data Input Inter-
face and the Receive Payload Data Output Interface to operate in either the
Serial-Mode or the Nibble/Parallel-Mode.
Setting this input pin "High" configures the Transmit and Receive Terminal Inter-
faces to operate in the Nibble/Parallel-Mode. In this mode, the Transmit Payload
Data Input Interface block accepts the outbound payload data from the Terminal
Equipment in a nibble-parallel manner via the TxNib[3:0] input pins. Further, the
Receive Payload Data Output Interface block outputs the inbound payload data
to the Terminal Equipment in a nibble-parallel manner via the RxNib[3:0] output
pin.
Setting this input pin "Low" configures the Transmit and Receive Terminal Inter-
faces to operate in the Serial Mode. In this mode, the Transmit Payload Data
Input Interface block accepts the outbound payload data from the Terminal
Equipment in a serial manner via the TxSer input pin. Further, the Receive Pay-
load Data Output Interface block outputs the inbound payload data to the Termi-
nal Equipment in a serial manner via the RxSer output pin.
I Reset Input:
When this active-low signal is asserted, the Framer is asynchronously reset.
Additionally, all outputs are tri-stated and all on-chip registers are reset to their
default values.
I Motorola/Intel Processor Interface Select Mode:
This input pin allows the user to configure the Microprocessor Interface to inter-
face with either a Motorola-type or Intel-type microprocessor/microcontroller.
Tying this input pin to VCC configures the microprocessor interface to operate in
the Motorola mode (e.g., the Framer can be readily interfaced to a Motorola type
local microprocessor). Tying this input pin to GND configures the Microproces-
sor Interface to operate in the Intel Mode (e.g., the Framer can be readily inter-
faced to a Intel type local microprocessor).
I Chip Select Input:
This active-low input signal selects the Microprocessor Interface Section of the
Framer and enables READ/WRITE operations between the Local Microproces-
sor and the Framer on-chip registers and RAM locations.
I Write Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this active-
low input pin functions as the WR (Write Strobe) input signal from the µP. Once
this active-low signal is asserted, then the Framer latches the contents of the µP
Data Bus into the addressed register or RAM location within the Framer IC. In
the Intel Mode, data gets latched on the rising edge of WR.
R/W Input Pin (Motorola Mode):
When the Microprocessor Interface is operating in the Motorola Mode, this pin is
functionally equivalent to the R/W pin. In the Motorola Mode, a READ operation
occurs if this pin is at a logic "1". A WRITE operation occurs if this pin is at a
logic "0".
I Address Latch Enable/Address Strobe:
This input is used to latch the address present at the Microprocessor Interface
Address Bus, A(9:0), into the Framer Microprocessor Interface circuitry and to
indicate the start of a READ/WRITE cycle. This input is active-high in the Intel
Mode (MOTO = "Low") and active-low in the Motorola Mode (MOTO = "High").
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