XR72L52 Datasheet, PDF (430/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
RXE3 CONFIGURATION & STATUS REGISTER 1 - (E3, ITU-T G.832) (ADDRESS = 0X10)
BIT 7
BIT 6
RxPLDType[2:0]
BIT 5
RO
RO
RO
0
0
0
BIT 4
RxFERF
Algo
R/W
0
BIT 3
RxTMark
Algo
R/W
0
BIT 2
BIT 1
RxPLDExp[2:0]
BIT 0
RO
RO
RO
0
0
0
Writing a “0” into this bit-field causes the Receive E3 Framer block to declare a FERF condition, if it detects 3
consecutive incoming E3 frames, that have the FERF bit (within the MA byte) set to “1”.
Writing a “1” into this bit-field causes the Receive E3 Framer block to declare a FERF condition, if it detects 5
consecutive incoming E3 frames, that have the FERF bit (within the MA byte) set to “1”.
Whenever the Receive E3 Framer block declares a FERF condition, then it will do the following.
• Generate a Change in FERF Condition interrupt to the MIcroprocessor. Hence, the Receive E3 Framer
block will assert Bit 3 (FERF Interrupt Status) within the Rx E3 Framer Interrupt Status register - 2, as
depicted below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
1
BIT 2
BIT 1
BIP-8
Error Interrupt
Status
Framing
Byte Error
Interrupt
Status
RUR
RUR
0
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
• Set the Rx FERF bit-field, within the Rx E3 Configuration/Status Register to “1”, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
Rx LOF Algo
BIT 6
RxLOF
R/W
RO
0
0
BIT 5
RxOOF
RO
0
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
RxPld Unstab
RO
0
BIT 1
Rx
TMark
RO
0
BIT 0
RxFERF
RO
1
Clearing the FERF Condition
The Receive E3 Framer block will clear the FERF condition once it has received a User-Selectable number of
E3 frames is either 3 or 5 depending upon the value that has been written into Bit 4 (Rx FERF Algo) of the Rx
E3 Configuration/Status Register, as discussed above.
Whenever the Receive E3 Framer clears the FERF status, then it will do the following:
1. Generate a Change in the FERF Status Interrupt to the Microprocessor.
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