XR72L52 Datasheet, PDF (65/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
This Read/Write bit-field permits the user to configure the Framer chip to either declare an LOS condition,
based upon the Internal Circuit's criteria or not.
Setting this bit-field to "0", configures the Framer chip to NOT declare an LOS condition, based upon its own in-
ternal criteria.
Setting this bit-field to "1", configures the Framer chip to declare an LOS condition based upon its own internal
criteria.
The XRT72L52 Framer Chip declares an LOS condition anytime the ExtLOS pin (pin 78) is set "High" indepen-
dent of the setting of this bit-field.
NOTE: For more information on the device's internal criteria for Loss of Signal, refer to Section 4.3.2.5.1.
Bit 4 - RESET:
This Read/Write bit-field permits the user to command the Framer chip in the Software Reset state. If the
XRT72L52 Framer is commanded into this state, then each of the internal state machines which control Fram-
ing Alignment, will be reset.
This type of Reset is different from the Hardware Reset (achieved by pulsing the Reset input pin
"Low"). The Software Reset will NOT reset the contents of the registers back to their default values.
The Software Reset Command routine should be written to toggle this bit-field from “0” to “1” and back to “0”, to
permit the chip to exit the Software Reset state.
Bit 3 - Interrupt Enable Reset
This Read/Write bit-field permits the user to configure the Framer chip to automatically disable all Interrupts
that are activated. The purpose of this feature is to diagnose a fault condition that continuously generates an
interrupt condition from recursively generating interrupts. This can hang up the Microprocessor by forcing it to
continuously operate in the Interrupt Service Routine.
By invoking this feature the system is protected from these recursive interrupts. Once a given interrupt is gen-
erated and the Microprocessor executes its Interrupt Service Routine (e.g. by reading out the states of the var-
ious Interrupt Status Registers, etc.), that particular interrupt will automatically be disabled and will not be gen-
erated again until the Microprocessor goes back and enables this particular interrupt again.
Setting this bit-field to "0" configures the XRT72L52 Framer chip to NOT disable the Interrupt Enable Status, of
any interrupts, following their activation. This is the default setting.
Setting this bit to "1" configures the XRT72L52 Framer chip to automatically disable any interrupt that is acti-
vated. This feature is typically used for diagnostic puposes only.
Bit 2 - Frame Format Select
This Read/Write bit-field, along with the DS3/E3 select bit-field (bit 6 in this register) permits the user to select
the Framing Format that the XRT72L52 will operate in. The following table relates the states of this bit-field
and that of bit 6 to the selected framing format for this chip.
BIT 6 - DS3/E3
SELECT
0
BIT 2 - FRAME
FORMAT SELECT
0
SELECTED FRAMING
FORMAT
E3, ITU-T G.751
0
1
E3, ITU-T G.832
1
0
DS3, C-bit Parity
1
1
DS3, M13
Bits 1 & 0 - TimRefSel[1:0] - Timing Reference Select
49