XR72L52 Datasheet, PDF (157/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
The Transmit Section of the XRT72L52 uses the TxInClk signal as its timing reference and initiates DS3 frame
generation asynchronously with respect to any externally applied signal. The XRT72L52 pulses its TxFrame
output pin "High" whenever it is processing the very last bit-field within a given DS3 frame.
Sampling of payload data from the Terminal Equipment
In Mode 3, the XRT72L52 samples the data at the TxSer input pin on the rising edge of TxInClk.
Interfacing the Transmit Payload Data Input Interface block of the XRT72L52 to the Terminal Equipment
for Mode 3 Operation
This is illustrated in Figure 36.
FIGURE 36. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 3 (SERIAL/LOCAL-TIMED/FRAME-MASTER) OPERATION
D S 3 _ C lo c k _ In
D S 3 _D ata_O ut
T x_S tart_of_F ram e
D S 3_O v erhead_In d
4 4.736M H z
Clock Source
T x In C lk
TxSer
T xF ram e
T x O H _Ind
Term inal Equipm ent
N ib In tf
DS3 Fram er
Mode 3 Operation of the Terminal Equipment
In Figure 36, both the Terminal Equipment and the XRT72L52 are driven by an external 44.736MHz clock sig-
nal. This clock signal is connected to the DS3_Clock_In input pin of the Terminal Equipment and the TxInClk
input pin of the XRT72L52.
The Terminal Equipment serially outputs the payload data on its DS3_Data_Out output pin upon the rising
edge of the signal at the DS3_Clock_In input pin. The XRT72L52 latches the data residing on the TxSer input
pin on the rising edge of TxInClk.
The XRT72L52 pulses the TxFrame output pin "High" for one bit-period coincident while it is processing the
last bit-field within a given outbound DS3 frame. The Terminal Equipment is expected to monitor the TxFrame
signal from the XRT72L52 and to place the first bit within the very next outbound DS3 frame on the TxSer input
pin.
In this case, the XRT72L52 dictates exactly when the very next DS3 frame is generated.
The Terminal Equipment is expected to respond appropriately by providing the XRT72L52 with the first bit of
the new DS3 frame upon demand. In this mode the XRT72L52 is referred to as the Frame Master and the Ter-
minal Equipment is referred to as the Frame Slave.
Finally, the XRT72L52 pulses its TxOH_Ind output pin one bit-period prior to it processing a given overhead bit
within the outbound DS3 frame. Since the TxOH_Ind output pin of the XRT72L52 is electrically connected to
the DS3_Overhead_Ind whenever the XRT72L52 pulses the TxOH_Ind output pin "High", it also drives the
DS3_Overhead_Ind input pin of the Terminal Equipment "High". Whenever the Terminal Equipment detects
this pin toggling "High", it should delay transmission of the very next DS3 frame payload bit by one clock cycle.
141