XR72L52 Datasheet, PDF (76/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.3.2.13 Receive DS3 FEAC Register
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxFEAC[5:0]
Not Used
RO
RO
RO
RO
RO
RO
RO
RO
0
1
1
1
1
1
1
0
This Read/Write register contains the latest 6-bit FEAC code that has been received and validated by the Re-
ceive FEAC Processor. The contents of this register will be cleared if the previously validated code has been
removed by the FEAC Processor.
NOTES:
1. For more information on the operation of the Receive FEAC Processor, refer to Section 4.3.3.1.
2. This register is only valid if the Channel has been configured to operate in the DS3, C-bit Parity Framing format.
2.3.2.14 Receive DS3 FEAC Interrupt Enable/Status Register
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FEAC Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
RO
RO
RO
RO
R/W
RUR
R/W
RUR
0
0
0
0
0
0
0
0
Bit 4 - FEAC Valid
This Read Only bit is set to "1" when an incoming FEAC Message Code has been validated by the Receive
DS3/E3 Framer block. This bit is cleared to "0" when the FEAC code is removed.
NOTE: For more information on the role of this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
Bit 3 - RxFEAC Remove Interrupt Enable
This Read/Write bit-field permits the user to enable/disable the RxFEAC Removal interrupt. Writing a "1" to
this bit enables this interrupt. Likewise, writing a "0" to this bit-field disables this interrupt.
NOTE: For more information on the role of this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
Bit 2 - RxFEAC Remove Interrupt Status
A "1" in this Reset-upon-Read bit-field indicates that the most recently received and validated FEAC Message
has now been removed by the Receive FEAC Processor. The Receive FEAC Processor will remove a validat-
ed FEAC message if 3 out of the last 10 received FEAC messages differ from the latest valid FEAC Message.
NOTE: For more information on this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
Bit 1 - RxFEAC Valid Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the Rx FEAC Valid interrupt. Writing a "1" to this
bit-field enables this interrupt. Whereas, writing a "0" disables this interrupt. The value of this bit-field is "0" fol-
lowing power up or reset.
NOTE: For more information on this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
Bit 0 - RxFEAC Valid Interrupt Status
A "1" in this Reset-upon-Read bit-field indicates that a newly received FEAC Message has been validated by
the Receive FEAC Processor.
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