XR72L52 Datasheet, PDF (128/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
1. For DS3 applications, the Frame-Parity Errors - One Second Accumulator” register contains the number of P-bit
errors that have been detected in the last one-second sampling period.
2. For E3, ITU-T G.751 applications, the Frame-Parity Error - One Second Accumulator” register contains the number
of BIP-4 errors that have been detected in the last one-second sampling period.
3. For E3, ITU-T G.832 applications, the Frame-Parity Error - One Second Accumulator register contains the number
of BIP-8 errors that have been detected in the last one-second sampling period.
2.3.8.17 One-Second Frame CP-Bit Error Accumulator Register - MSB
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error Count - High Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register, along with the Frame CP-Bit Error - One-Second Accumulator Register - LSB (Ad-
dress = 0x73) contains a 16-bit representation of the number of CP Bit Errors tjhat have been detected by the
Receive DS3/E3 Framer block, within the last one-second sampling period. This register contains the MSB (or
Upper Byte) value of this 16-bit expression.
NOTE: This register is only active if the Channel has been configured to operate in the DS3, C-bit Parity framing format.
2.3.8.18 One-Second Frame CP-Bit Error Accumulator Register - LSB
FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error Count - Low Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register, along with the Frame CP-Bit Error - One-Second Accumulator Register - MSB (Ad-
dress = 0x72) contains a 16-bit representation of the number of CP Bit Errors tjhat have been detected by the
Receive DS3/E3 Framer block, within the last one-second sampling period. This register contains the LSB (or
Lower Byte) value of this 16-bit expression.
NOTE: This register is only active if the Channel has been configured to operate in the DS3, C-bit Parity framing format.
2.3.8.19 Line Interface Drive Register
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ILOOP
Not Used
REQB
TAOS
ENCODIS
TxLEV
RLOOP
LLOOP
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - ILOOP (Internal Remote Loop-back)
This Read/Write bit-field permits the user to configure the corresponding channel (within the XRT72L52) to op-
erate in the Internal Remote Loop-back Mode. Once the user configures the channel to operate in this remote
loop-back mode, then the RxPOSn, RxNEGn and RxLineClk signals will be routed directly to the TxPOSn, Tx-
NEGn and TxLineClk signals.
Setting this bit-field to “1” configures the channel to operate in the Remote Loop-Back Mode.
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