XR72L52 Datasheet, PDF (121/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.3.7.3 Transmit E3 LAPD Status and Interrupt Register (ITU-T G.751)
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Not Used
TXDL Start TXDL Busy
RO
RO
RO
RO
R/W
RO
0
0
0
0
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
0
XRT72L52
REV. 1.0.1
BIT 0
TxLAPD
Interrupt
Status
RUR
0
Bit 3 - TxDL Start
This Read/Write bit-field permits the user to command the LAPD Transmitter to do the following.
• Read in the PMDL Header and Message from the Transmit LAPD Message Buffer. (80 or 86 bytes)
• Compute the frame check sequence word (16 bit value)
• Insert the Frame Check Sequence value into the 2 octet slot after the payload section of the Message.
• Perform zero stuffing between 0x7E flag bytes. (81 or 87 bytes)
• Send LAPD Message single bit at a time in the “N” bit position.
• Source of “N” bits should be set as transmit LAPD controller, (bits 4 and 3 set to “10” in 0x30).
A "0" to "1" transition, in this bit-field commands the LAPD Transmitter to initiate the above-mentioned proce-
dure.
NOTE: Once the LAPD Transmitter has been commanded to start transmission, the LAPD Transmitter will repeat the
above-mentioned process once each second and will insert flag sequence octets into the outbound LAPD channel, during
the idle periods between transmissions.
Bit 2 - TxDL Busy
This Read-Only bit-field permits the user to poll or monitor the status of the LAPD Transmitter to see if it has
completed its transmission of the LAPD Message frame. The LAPD Transmitter will set this bit-field to "1",
while it is in the process of transmitting the LAPD Message frame. However, the LAPD Transmitter will clear
this bit-field to "0" once it has completed its transmission of the LAPD Message frame.
Bit 1 - TxLAPD Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the LAPD Message frame Transmission Com-
plete interrupt.
Writing a "0" to this bit-field disables this interrupt. Writing a "1" to this bit-field enables this interrupt.
Bit 0 - TxLAPD Interrupt Status
This Reset-upon-Read bit-field permits the user to determine if the LAPD Message Frame Transmission Com-
plete interrupt has occurred since the last read of this register. If this bit-field contains a "1" then the LAPD
Message Frame Transmission Complete interrupt has occurred since the last read of this register. Conversely,
if this bit-field contains a "0" then it has not.
2.3.7.4 Transmit E3 Service Bits Register (ITU-T G.751)
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
A-Bit
N-Bit
RO
RO
RO
RO
RO
RO
R/W
R/W
0
0
0
0
0
0
0
0
Bit 1 - A-Bit
105