XR72L52 Datasheet, PDF (367/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 146. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT72L52 AND THE TERMINAL EQUIPMENT (FOR MODE 1 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
Payload[4238] Payload[4239]
FA1, Bit 7
FA1, Bit 6
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxSer
Payload[4238] Payload[4239]
TxFrame
TxOH_Ind
FA1, Bit 7
FA1, Bit 6
E3 Frame Number N
Note: TxFrame pulses high to denote
E3 Frame Boundary.
Note: TxOH_Ind pulses high for
16 bit periods in order to
denote Overhead Data
(e.g., the FA1 and FA2 bytes)
E3 Frame Number N + 1
Note: The FA1 byte will not be processed by the
Transmit Payload Data Input Interface.
How to configure the XRT72L52 into the Serial/Loop-Timed/Non-Overhead Interface Mode
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit fields (within the Framer Operating Mode Register) to "00" as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local Loop-back
BIT 6
DS3/E3*
R/W
R/W
0
0
BIT 5
Internal LOS
Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
Interrupt
Enable Reset
R/W
1
BIT2
Frame Format
R/W
1
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
0
3. Interface the XRT72L52, to the Terminal Equipment, as illustrated in Figure 145.
6.2.1.2 Mode 2 - The Serial/Local-Timed/Frame-Slave Mode Behavior of the XRT72L52
If the XRT72L52 has been configured to operate in this mode, then the XRT72L52 will function as follows.
A. Local Timing - Uses the TxInClk signal as the Timing Reference
In this mode, the Transmit Section of the XRT72L52 will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT72L52 will receive the E3 payload data, in a serial manner, via the TxSer input pin. The Transmit Pay-
load Data Input Interface (within the XRT72L52) will latch this data into its circuitry, on the rising edge of the Tx-
InClk input clock signal.
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