XR72L52 Datasheet, PDF (74/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.3.2.11 Receive DS3 Interrupt Status Register
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
1
0
0
0
0
0
0
Bit 7 - CP Bit Error Interrupt Status
This Reset-upon-Read bit-field indicates whether or not the Detection of CP Bit Error Interrupt has occurred
since the last read of this register. This bit-field will be “0” if the Detection of CP-Bit Error Interrupt has not oc-
curred since the last read of this register. Conversely, this bit-field will be set to “1” if this interrupt has occurred
since the last read of this register. The Detection of CP Bit Error Interrupt will occur if the Receive DS3/E3
Framer block detects a CP bit-error in the incoming DS3 frame.
NOTE: This bit-field is only valid if the channel has been configured to operate in the DS3, C-bit Parity Framing format.
Bit 6 - LOS Interrupt Status
This Reset Upon Read bit will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in the
LOS Status condition, since the last time this register was read. This bit-field will be asserted under either of
the following conditions:
For DS3 Applications
1. When the Receive DS3/E3 Framer block detects the occurrence of an LOS Condition (e.g., the occurrence
of 180 consecutive spaces in the incoming DS3 data stream), and
2. When the Receive DS3/E3 Framer block detects the end of an LOS Condition (e.g., when the Receive
DS3 Framer detects 60 mark pulses in the last 180 bit periods).
NOTE: For more information in the LOS of Signal (LOS) Alarm, refer to Section 4.3.2.5.1.
Bit 5 - AIS Interrupt Status
This Reset Upon Read bit field will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in
the AIS condition, since the last time this register was read. This bit-field will be asserted under either of the
following two conditions:
1. When the Receive DS3/E3 Framer block first detects an AIS Condition in the incoming DS3 data stream,
and
2. When the Receive DS3/E3 Framer block has detected the end of an AIS Condition.
The local µP can determine the current state of the AIS condition by reading bit 7 of the Rx DS3 Configuration
and Status Register (Address = 0x10).
NOTE: For more information on the AIS Condition, refer to Section 4.3.2.5.2.
Bit 4 - Idle Interrupt Status
This Reset Upon Read bit-field is set to "1" when the Receive DS3/E3 Framer block detects a Change in the
Idle Condition in the incoming DS3 data stream. Specifically, the Receive DS3/E3 Framer block will assert this
bit-field under either of the following two conditions:
1. When the Receive DS3/E3 Framer block detects the onset of the Idle Condition and
2. When the Receive DS3/E3 Framer block detects the end of the Idle Condition.
The local µP can determine the current state of the Idle condition by reading bit 5 of the Rx DS3 Configuration
and Status Register (Address = 0x10).
NOTE: For more information into the Idle Condition, refer to Section 4.3.2.5.3.
Bit 3 - FERF Interrupt Status
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