XR72L52 Datasheet, PDF (42/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
CONDITIONS
t₄₂ Period of RxLineClk
22.36
ns DS3 Applications
29.10
ns
Receive Payload Data Output Interface Timing - Serial Mode Operation (See Figure 13)
t₅₀ Rising edge of RxClk to Payload Data (RxSer) out-
put delay
13
ns
16
ns
t₅₁ Rising edge of RxClk to RxFrame output delay
13
ns
E3 Applications
DS3 Applications
E3 Applications
DS3 Applications
t₅₂ Rising edge of RxClk to RxOHInd output delay.
16
ns E3 Applications
13
ns DS3 Applications
16
ns E3 Applications
Receive Payload Data Output Interface Timing - Nibble Mode Operation (see Figure 14)
t₅₃
Falling edge of RxClk to rising edge of RxFrame out-
put delay
2.1
ns
t₅₄
Falling edge of RxClk to rising edge of RxNib[3:0]
output delay
2
ns
Receive Overhead Data Output Interface Timing - Method 1 - Using RxOHClk (see Figure 15)
t_59A ^{Falling edge of RxOHClk to RxOHFrame output}
20
23
ns
DS3 Applications
25
t_59B ^{Falling edge of RxOHClk to RxOH output delay}
20
0
ns E3 Applications
23
ns DS3 Applications
25
0
ns E3 Applications
Receive Overhead Data Output Interface Timing - Method 2 - Using RxOHEnable (see Figure 16)
t₆₀ Rising edge of RxOutClk to rising edge of
2
9.4
ns
RxOHEnable delay.
t_60A Rising edge of RxOHFrame to rising edge of
RxOHEnable delay
88
ns ^{DS3 Applications}
E3, ITU-T G.832
224
ns
Applications
t_60B RxOH Data Valid to rising edge of
RxOHEnable delay
E3, ITU-T G.751
28
ns
Applications
88
ns ^{DS3 Applications}
85
ns
E3, ITU-T G.832
Applications
Microprocessor Interface - Intel (See Figure 17)
t₆₄ CS Setup Time to ALE_AS Low
E3, ITU-T G.751
28
ns
Applications
0
ns
26