XR72L52 Datasheet, PDF (155/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 34. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 2 (SERIAL/LOCAL-TIMED/FRAME-SLAVE) OPERATION
D S 3 _ C lo c k _ In
D S 3 _D ata_O ut
T x_S tart_of_F ram e
D S 3_O v erhead_In d
4 4.736M H z
Clock Source
T x In C lk
TxSer
T xF ram eR ef
T x O H _Ind
N ib In t
Term inal Equipm ent
DS3 Fram er
Mode 2, Operation of the Terminal Equipment
As shown in Figure 34, both the Terminal Equipment and the XRT72L52 are driven by an external 44.736MHz
clock signal. The Terminal Equipment receives the 44.736MHz clock signal via its DS3_Clock_In input pin and
the XRT72L52 Framer receives the 44.736MHz clock signal via the TxInClk input pin.
The Terminal Equipment serially outputs the payload data of the outbound DS3 data stream via the
DS3_Data_Out output pin upon the rising edge of the signal at the DS3_Clock_In input pin.The DS3_Data_Out
output pin of the Terminal Equipment is electrically connected to the TxSer input pin.
The XRT72L52 Framer latches the data residing on the TxSer input line on the rising edge of the TxInClk sig-
nal.
The Terminal Equipment has the responsibility of providing the framing reference signal by pulsing its
Tx_Start_of_Frame output signal and the TxFrameRef input pin of the XRT72L52 "High" for one-bit period, co-
incident with the first bit of a new DS3 frame. Once the XRT72L52 detects the rising edge of the input at its Tx-
FrameRef input pin, it begins generation of a new DS3 frame.
In this case, the Terminal Equipment is controlling the start of Frame Generation and is referred to as the
Frame Master. Since the XRT72L52 does not control the generation of a new DS3 frame, but is rather driven
by the Terminal Equipment it is referred to as the Frame Slave.
If the XRT72L52 is configured to operate in Mode 2, it is imperative that the Tx_Start_of_Frame or TxFrameRef
signal is synchronized to the TxInClk input clock signal.
Finally, the XRT72L52 pulses its TxOH_Ind output pin one bit-period prior to it processing a given overhead bit
within the outbound DS3 frame. Since the TxOH_Ind output pin of the XRT72L52 is electrically connected to
the DS3_Overhead_Ind whenever the XRT72L52 pulses the TxOH_Ind output pin "High", it also drives the
DS3_Overhead_Ind input pin of the Terminal Equipment "High". Whenever the Terminal Equipment detects
this pin toggling "High" it should delay transmission of the very next DS3 frame payload bit by one clock cycle.
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