XR72L52 Datasheet, PDF (251/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
To enable or disable the Change of State on Receive AIC Interrupt, write the appropriate value into Bit 2 (AIC
Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change of State on Receive AIC Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request Output pin (Int) by driving it "High".
• It will set Bit 2 (AIC Interrupt Status), within the Rx DS3 Interrupt Status Register, to “1”, as indicated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
CP-Bit Error
Interrupt
Status
RUR
0
BIT 6
LOS
Interrupt
Status
RUR
0
BIT 5
AIS
Interrupt
Status
RUR
0
BIT 4
Idle Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
AIC
Interrupt
Status
RUR
1
BIT 1
OOF
Interrupt
Status
RUR
0
BIT 0
P-Bit Error
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters this interrupt, it should do the following.
• It should continue to check the state of the AIC bit, in order to see if this change is constant.
• If this change is constant, then the user should configure the XRT72L52 Framer IC to operate in the M13
framing format, if the AIC bit-field is “0”.
• Conversely, if the AIC bit-field is “1”, then the user should configure the XRT72L52 Framer IC to operate in
the C-bit Parity framing format.
4.3.6.2.7 The Detection of P-Bit Error Interrupt
If the Detection of P-Bit Error Interrupt is enabled, then the XRT72L52 Framer IC will generate an interrupt,
anytime the Receive DS3 Framer block has detected a P-bit error, within the incoming DS3 data stream.
Enabling and Disabling the Detection of P-Bit Error Interrupt:
235