XR72L52 Datasheet, PDF (198/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
In general the B3ZS line code behaves just like AMI with the exception of the case when a long string of con-
secutive zeros occur on the line. Any string of 3 consecutive zeros will be replaced with either a 00V or a B0V
where B refers to a Bipolar pulse (e.g., a pulse with a polarity that is compliant with the AMI coding rule). And
V refers to a Bipolar Violation pulse (e.g., a pulse with a polarity that violates the alternating polarity scheme of
AMI.) The decision between inserting an 00V or a B0V is made to insure that an odd number of Bipolar (B)
pulses exist between any two Bipolar Violation (V) pulses. Figure 57 presents a timing diagram that illustrates
examples of B3ZS encoding.
FIGURE 57. ILLUSTRATION OF TWO EXAMPLES OF B3ZS ENCODING
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
TxPOS
TxNEG
00 V
Line Signal
B 0V
The user chooses between AMI or B3ZS line coding by writing to bit 4 of the I/O Control Register (Address =
0x01), as shown below.
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 30 relates the content of this bit-field to the Bipolar Line Code that DS3 Data will be transmitted and re-
ceived at.
TABLE 30: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK
BIT 4
0
1
BIPOLAR LINE CODE
B3ZS
AMI
NOTES:
1. This bit is ignored if the Unipolar mode is selected.
2. This selection also effects the operation of the Receive DS3 LIU Interface block
4.2.5.2 TxLineClk Clock Edge Selection
The Framer also allows the user to specify whether the DS3 output data (via TxPOS and/or TxNEG output
pins) is to be updated on the rising or falling edges of the TxLineClk signal. The purpose of this feature is to in-
sure that the Framer will always be able to output data to the LIU IC, in such a way that the LIU set-up and hold
time requirements can always be met. This selection is made by writing to bit 2 of the I/O Control Register, as
depicted below.
182