XR72L52 Datasheet, PDF (216/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
NAIS - NVALID < 0.
In other words, once the Receive DS3 Framer block has detected a sufficient number of normal (or Non-AIS)
M-frames, such that this Up/Down counter reaches zero, then the Receive DS3 Framer block will clear the AIS
Condition indicators. The Receive DS3 Framer block will inform the µC/µP of this negation of the AIS Status
by generating a Change in AIS Status interrupt.
4.3.2.5.3 The Idle (Condition) Alarm
The Receive DS3 Framer block will identify and declare an Idle Condition if it receives a sufficient number of
M-Frames that meets all of the following conditions.
• Valid M-bits, F-bits, and P-bits
• The 3 CP-bits (in F-Frame #3) are zeros.
• The X-bits are set to 1
• The payload portion of the DS3 Frame exhibits a repeating 1100... pattern.
The Receive DS3 Framer block circuitry includes an Up/Down Counter that is used to track the number of M-
frames that have been identified as exhibiting the Idle Condition by the Receive DS3 Framer block. The con-
tents of this counter are set to zero upon reset or power up. This counter is then incremented whenever the
Receive DS3 Framer block detects an Idle-type M-frame. The counter is decremented, or kept at zero if a non-
Idle M-frame is detected. If the Receive DS3 Framer block detects a sufficient number of Idle-type M-frames,
such that the counter reaches the number 63, then the Receive DS3 Framer block will declare the Idle Condi-
tion. Explained another way, the Receive DS3 Framer block will declare an Idle Condition if the number of Idle-
Pattern M-frames is detected such that it meets the following conditions.
NIDLE - NVALID > 63,
where:
NIDLE = the number of M-frames containing the Idle Pattern
NVALID = the number of M-frames not exhibit the Idle Pattern
Anytime the contents of this Up/Down Counter reaches the number 63, then the Receive DS3 Framer block
will:
1. Set Bit 5 (RxIdle) within the Rx DS3 Configuration and Status Register, to "1" as depicted below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
RxAIS
RO
X
BIT 6
RxLOS
RO
X
BIT 5
RxIdle
RO
1
BIT 4
RxOOF
RO
X
BIT 3
Reserved
RO
X
BIT2
BIT 1
BIT 0
Framing on F-Sync Algo M-Sync Algo
Parity
R/W
R/W
R/W
X
X
X
2. Generate a Change in Idle Status Interrupt Request to the local µP/µC.
The Receive DS3 Framer block will clear the Idle Condition if it has detected a sufficient number of Non-Idle M-
frames, such that this Up/Down Counter reaches the value 0.
4.3.2.5.4 The Detection of (FERF) or Yellow Alarm Condition
The Receive DS3 Framer block will identify and declare a Yellow Alarm condition or a Far-End Receive Failure
(FERF) condition, if it starts to receive DS3 frames with both of its X-bits set to 0.
When the Receive DS3 Framer block detects a FERF condition in the incoming DS3 frames, then it will then do
the following.
1. It will assert the RxFERF (bit-field 4) within the Rx DS3 Status Register, as depicted below.
200