XR72L52 Datasheet, PDF (11/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Operation)...................................................................................................................................................... 260
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 260
5.2.2 The Transmit Overhead Data Input Interface....................................................................................... 260
Figure 100. The Transmit Overhead Data Input Interface block ................................................................................... 261
TABLE 44: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE XRT72L52 IC
261
TABLE 45: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................ 263
Figure 101. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 1)..... 264
TABLE 46: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE TXOHFRAME WAS LAST
SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED ......................................................... 265
Figure 102. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L52 in order to
configure the XRT72L52 to transmit a Yellow Alarm to the remote terminal equipment ............................... 266
TABLE 47: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................ 267
Figure 103. The Terminal Equipment being interfaced to the Transmit Overhead Data Input Interface (Method 2)..... 268
TABLE 48: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE OF THE
TXOHFRAME PULSE) TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L52 ...................... 269
Figure 104. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L52 and the Terminal
Equipment (for Method 2).............................................................................................................................. 270
5.2.3 The Transmit E3 HDLC Controller ....................................................................................................... 270
Figure 105. LAPD Message Frame Format.................................................................................................................. 271
TABLE 49: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFORMATION PAYLOAD
272
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 272
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ....................................................... 273
TABLE 50: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ............................................. 273
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................................... 273
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ....................................................... 274
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)........................................................ 274
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)........................................................ 275
Figure 106. Flow Chart Depicting how to use the LAPD Transmitter............................................................................ 276
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ....................................................................... 277
5.2.4 The Transmit E3 Framer Block ............................................................................................................ 277
Figure 107. The Transmit E3 Framer Block and the associated paths to other Functional Blocks............................... 278
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 279
TABLE 51: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIGURATION REGISTER,
AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ........................................................................... 279
TABLE 52: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION REGISTER, AND
THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION .................................................................................. 280
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 280
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35).................................................................................. 281
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 281
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 281
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48)..................................................................... 282
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49)..................................................................... 282
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)........................................................................ 282
5.2.5 The Transmit E3 Line Interface Block .................................................................................................. 282
Figure 108. Interfacing the XRT72L52 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................. 283
Figure 109. The Transmit E3 LIU Interface block ......................................................................................................... 284
Figure 110. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit E3 LIU Interface is
operating in the Unipolar Mode ..................................................................................................................... 284
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 285
TABLE 53: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE UNI I/O CONTROL REGISTER
AND THE TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE ...................................................................... 285
Figure 111. Illustration of AMI Line Code ...................................................................................................................... 286
Figure 112. Illustration of two examples of HDB3 Encoding ......................................................................................... 286
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 287
TABLE 54: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE
THAT IS OUTPUT BY THE TRANSMIT E3 LIU INTERFACE BLOCK .......................................................................... 287
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 287
TABLE 55: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE
TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ............................................................. 287
Figure 113. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
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