XR72L52 Datasheet, PDF (248/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
1. It should determine the current state of the AIS condition. Recall, that this interrupt can generated, when-
ever the XRT72L52 Framer declares or clears the AIS defects. Hence, the current state of the AIS defect
can be determined by reading the state of Bit 7 (RxAIS), within the RxDS3 Configuration & Status Regis-
ters, as illustrated below
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)
BIT 7
RxAIS
RO
0
BIT 6
RxLOS
RO
0
BIT 5
RxIdle
RO
0
BIT 4
RxOOF
RO
0
BIT 3
Reserved
RO
X
BIT 2
Framing On
Parity
R/W
0
BIT 1
FSync
Algo
R/W
0
BIT 0
MSync
Algo
R/W
0
If the AIS Condition is TRUE
1. The Local Terminal Equipment should transmit a FERF (Far-End Receive Failure) to the Remote Terminal
Equipment. The XRT72L52 Framer IC automatically supports this action via the FERF-upon-AIS feature.
2. It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE), to the Remote Terminal,
indicating that a Service Affecting condition has been detected in the Local Terminal Equipment.
If the AIS Condition is FALSE
1. The Local Terminal Equipment should cease transmitting a FERF (Far-End Receive Failure) indicator to
the Remote Terminal Equipment. The XRT72L52 Framer IC automatically supports this action via the
FERF-upon-AIS feature.
2. It should transmit the appropriate FEAC Message (per Bellcore GR-499-CORE) to the Remote Terminal,
indicates that the Service Affecting condition no longer exists.
4.3.6.2.4 The Change of State of Receive Idle Interrupt
If the Change of State on Receive Idle Interrupt is enabled, then the XRT72L52 Framer IC will generate an in-
terrupt in response to either of the following conditions.
1. When the XRT72L52 Framer IC detects an Idle pattern, in the incoming DS3 data stream, and
2. When the XRT72L52 Framer IC no longer detects the Idle pattern in the incoming DS3 data stream.
Conditions causing the XRT72L52 Framer IC to declare an Idle condition
• If the Receive DS3 Framer block (within the XRT72L52 Framer IC) detects at least 63 DS3 frames, which
contains the Idle pattern.
Conditions causing the XRT72L52 Framer IC to clear the Idle condition.
• Whenever, the Receive DS3 Framer block detects 63 DS3 frames, which do not contain the Idle pattern.
Enabling and Disabling the Change of State on Receive Idle Interrupt:
To enable or disable the Change of State on Receive Idle Interrupt, write the appropriate value into Bit 4 (Idle
Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
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