XR72L52 Datasheet, PDF (272/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
3. Interface the XRT72L52, to the Terminal Equipment, as illustrated in Figure 94.
NOTE: The XRT72L52 Framer IC cannot support the Framer Local Loop-back Mode of operation, while operating in Mode
4. The user must configure the XRT72L52 Framer IC into any of the following modes prior to configuring the Framer Local
Loop-back Mode operation.
• Mode 2 - Serial/Local-Timed/Frame-Slave Mode
• Mode 3 - Serial/Local-Timed/Frame-Master Mode
• Mode 5 - Nibble-Parallel/Local-Timed/Frame-Slave Mode
• Mode 6 - Nibble-Parallel/Local-Timed/Frame-Master Mode.
For more detailed information on the Framer Local Loop-back Mode, please see Section 7.0.
5.2.1.5 Mode 5 - The Nibble-Parallel/Local-Timed/Frame-Slave Interface Mode Behavior of the
XRT72L52
If the XRT72L52 has been configured to operate in this mode, then the XRT72L52 will function as follows:
A. Local-Timed - Uses the TxInClk signal as the Timing Reference
In this mode, the Transmit Section of the XRT72L52 will use the TxInClk signal at its timing reference. Further,
the chip will internally divide the TxInClk clock signal by a factor of 4 and will output this divided clock signal via
the TxNibClk output pin. The Transmit Terminal Equipment Input Interface block (within the XRT72L52) will
use the rising edge of the TxNibClk signal, to latch the data, residing on the TxNib[3:0] into its circuitry.
B. Nibble-Parallel Mode
The XRT72L52 will accept the E3 payload data, from the Terminal Equipment, in a parallel manner, via the Tx-
Nib[3:0] input pins. The Transmit Terminal Equipment Input Interface will latch this data into its circuitry, on the
rising edge of the TxNibClk output signal.
C. Delineation of outbound E3 Frames
The Transmit Section will use the TxInClk input signal as its timing reference and will use the TxFrameRef in-
put signal as its Framing Reference (e.g., the Transmit Section of the XRT72L52 initiates frame generation up-
on the rising edge of the TxFrameRef signal).
D. Sampling of payload data, from the Terminal Equipment
In Mode 5, the XRT72L52 will sample the data, at the TxNib[3:0] input pins, on the third rising edge of the TxIn-
Clk clock signal, following a pulse in the TxNibClk signal (see Figure 96).
NOTE: The TxNibClk signal, from the XRT72L52 operates nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
Interfacing the Transmit Payload Data Input Interface block of the XRT72L52 to the Terminal Equipment
for Mode 5 Operation
Figure 96 presents an illustration of the Transmit Payload Data Input Interface block (within the XRT72L52) be-
ing interfaced to the Terminal Equipment, for Mode 5 Operation.
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