XR72L52 Datasheet, PDF (382/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TABLE 68: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE
XRT72L52 IC
OVERHEAD BIT
TR - Bit 0
MA - Bit 7
INTERNALLY GENERATED
No
Yes
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
Yes
Yes
BUFFER/REGISTER
ACCESSIBLE
Yes
Yes
MA - Bit 6
Yes
Yes
Yes
MA - Bit 5
Yes
Yes
Yes
MA - Bit 4
Yes
Yes
Yes
MA - Bit 3
Yes
Yes
Yes
MA - Bit 2
Yes
Yes
Yes
MA - Bit 1
Yes
Yes
Yes
MA - Bit 0
Yes
Yes
Yes
NR - Bit 7
No
Yes
Yes
NR - Bit 6
No
Yes
Yes
NR - Bit 5
No
Yes
Yes
NR - Bit 4
No
Yes
Yes
NR - Bit 3
No
Yes
Yes
NR - Bit 2
No
Yes
Yes
NR - Bit 1
No
Yes
Yes
NR - Bit 0
No
Yes
Yes
GC - Bit 7
No
Yes
Yes
GC - Bit 6
No
Yes
Yes
GC - Bit 5
No
Yes
Yes
GC - Bit 4
No
Yes
Yes
GC - Bit 3
No
Yes
Yes
GC - Bit 2
No
Yes
Yes
GC - Bit 1
No
Yes
Yes
GC - Bit 0
No
Yes
Yes
NOTES:
1. The XRT72L52 contains mask register bits that permit the user to alter the state of the internally generated value
for these bits.
2. The Transmit LAPD Controller/Buffer can be configured to be the source of the NR or GC bytes, within the Out-
bound E3 data stream.
In all, the Transmit Overhead Data Input Interface permits the user to insert overhead data into the Outbound
E3 frames via the following two different methods.
• Method 1 - Using the TxOHClk clock signal
• Method 2 - Using the TxInClk and the TxOHEnable signals.
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