XR72L52 Datasheet, PDF (308/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
The Receive Section of the XRT72L52 will via the Receive E3 LIU Interface Block receive timing and data in-
formation from the incoming E3 data stream. The E3 Timing information will be received via the RxLineClk in-
put pin and the E3 data information will be received via the RxPOS and RxNEG input pins. The Receive E3
LIU Interface block is capable of receiving E3 data pulses in unipolar or bipolar format. If the Receive E3 fram-
er is operating in the bipolar format, then it can be configured to decode either AMI or HDB3 line code data.
Each of these input formats and line codes will be discussed in detail, below.
5.3.1.1 Unipolar Decoding
If the Receive E3 LIU Interface block is operating in the Unipolar (single-rail) mode, then it will receive the Sin-
gle Rail NRZ E3 data pulses via the RxPOS input pin. The Receive E3 LIU Interface block will also receive its
timing signal via the RxLineClk signal.
NOTE: The RxLineClk signal will function as the timing source for the entire Receive Section of the XRT72L52.
No data pulses will be applied to the RxNEG input pin. The Receive E3 LIU Interface block receives a logic "1"
when a logic "1" level signal is present at the RxPOS pin, during the sampling edge of the RxLineClk signal.
Likewise, a logic "0" is received when a logic "0" level signal is applied to the RxPOS pin. Figure 117 presents
an illustration of the behavior of the RxPOS, RxNEG and RxLineClk input pins when the Receive E3 LIU Inter-
face block is operating in the Unipolar mode.
FIGURE 117. BEHAVIOR OF THE RXPOS, RXNEG AND RXLINECLK SIGNALS DURING DATA RECEPTION OF UNIPO-
LAR DATA
Data _{1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1}
RxPOS
1 10
01
RxNEG
RxLineClk
The user can configure the Receive E3 LIU Interface block to operate in either the Unipolar or the Bipolar
Mode by writing the appropriate data to the I/O Control Register, as depicted below.
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable TxLOC
BIT 6
LOC
R/W
RO
1
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup*
R/W
0
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 56 relates the value of this bit-field to the Receive E3 LIU Interface Input Mode.
TABLE 56: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 3
0
1
RECEIVE E3 LIU INTERFACE INPUT MODE
Bipolar Mode (Dual Rail): AMI or HDB3 Line Codes are Transmitted and Received.
Unipolar Mode (Single Rail) Mode of transmission and reception of E3 data is selected.
NOTES:
1. The default condition is the Bipolar Mode.
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