XR72L52 Datasheet, PDF (265/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
5.2.1.2 Mode 2 - The Serial/Local-Timed/Frame-Slave Mode Behavior of the XRT72L52
If the XRT72L52 has been configured to operate in this mode, then the XRT72L52 will function as follows.
A. Local-Timed - Uses the TxInClk signal as the Timing Reference
In this mode, the Transmit Section of the XRT72L52 will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT72L52 will receive the E3 payload data, in a serial manner, via the TxSer input pin. The Transmit Pay-
load Data Input Interface (within the XRT72L52) will latch this data into its circuitry, on the rising edge of the Tx-
InClk input clock signal.
C. Delineation of outbound E3 frames (Frame Slave Mode)
The Transmit Section of the XRT72L52 will use the TxInClk input as its timing reference, and will use the Tx-
FrameRef input signal as its framing reference. In other words, the Transmit Section of the XRT72L52 will ini-
tiate frame generation upon the rising edge of the TxFrameRef input signal).
D. Sampling of payload data, from the Terminal Equipment
In Mode 2, the XRT72L52 will sample the data, at the TxSer input pin, on the rising edge of TxInClk.
Interfacing the Transmit Payload Data Input Interface block of the XRT72L52 to the Terminal Equipment
for Mode 2 Operation
Figure 90 presents an illustration of the Transmit Payload Data Input Interface block (within the XRT72L52) be-
ing interfaced to the Terminal Equipment, for Mode 2 operation.
FIGURE 90. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 2 (SERIAL/LOCAL-TIMED/FRAME-SLAVE) OPERATION
3 4.368M H z
Clock Source
E 3 _ C lo c k _ In
E 3_D ata_O ut
T x_S tart_of_F ram e
E 3_O v erhead_Ind
T x In C lk
TxSer
T xF ram eR ef
T x O H _Ind
N ib In tf
Term inal Equipm ent
E3 Fram er
Mode 2 Operation of the Terminal Equipment
As shown in Figure 90, both the Terminal Equipment and the XRT72L52 will be driven by an external
34.368MHz clock signal. The Terminal Equipment will receive the 34.368MHz clock signal via its E3_Clock_In
input pin, and the XRT72L52 Framer IC will receive the 34.368MHz clock signal via the TxInClk input pin.
The Terminal Equipment will serially output the payload data of the outbound E3 data stream, via the
E3_Data_Out output pin, upon the rising edge of the signal at the E3_Clock_In input pin.
NOTE: The E3_Data_Out output pin of the Terminal Equipment is electrically connected to the TxSer input pin
The XRT72L52 Framer will latch the data residing on the TxSer input line on the rising edge of the TxInClk sig-
nal.
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