XR72L52 Datasheet, PDF (434/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error
Interrupt
Status
RUR
1
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
0
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Finally, the Receive E3 Framer block will increment the PMON Parity Error Count registers. The byte format of
these registers are presented below.
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
Parity Error Count - Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
The user can determine the number of BIP-8 Errors that have been detected by the Receive E3 Framer block,
since the last read of these registers. These registers are reset-upon-read.
6.3.2.8 Processing of the Far-End-Block Error (FEBE) Bit-fields
Whenever the Receive E3 Framer detects an error in the incoming E3 frame, via EM byte verification, it will in-
form the Local Transmit E3 Framer of this fact. The Local Transmit E3 Framer will, in turn, notify the Remote
Terminal (e.g., the source of the errored E3 frame) by transmitting an E3 frame, with the FEBE bit-field (within
the MA byte) set to “1”.
If the Receive E3 Framer receives any E3 frame, with the FEBE bit-field set to “1”, then it will do the following.
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