XR72L52 Datasheet, PDF (433/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 186. ILLUSTRATION OF THE LOCAL RECEIVE E3 FRAMER BLOCK, RECEIVING AN E3 FRAME (FROM THE
REMOTE TERMINAL) WITH AN INCORRECT EM BYTE.
Local Terminal
Transmit E3
Framer
Receive E3
Framer
EM Byte
0x5A
Remote
Terminal
0x5B
Locally Calculated
EM Byte
FIGURE 187. ILLUSTRATION OF THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME (TO THE
REMOTE TERMINAL) WITH THE FEBE BIT (WITHIN THE MA BYTE-FIELD) SET TO “1”
Local Terminal
FEBE bit
x1xxxxxx
Transmit E3
Framer
Receive E3
Framer
MA Byte
Remote
Terminal
In additional to the FEBE bit-field signaling, the Receive E3 Framer block will generate the BIP-8 Error Interrupt
to the Microprocessor. Hence, it will set bit 2 (BIP-8 Error Interrupt Status) to “1”, as depicted below.
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