XR72L52 Datasheet, PDF (419/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
The Receive E3 LIU Interface block will also check the incoming E3 data stream for line code violations. For
example, when the Receive E3 LIU Interface block detects a valid bipolar violation (e.g., in HDB3 line code), it
will substitute four zeros into the binary data stream. However, if the bipolar violation is invalid, then an LCV
(Line Code Violation) is flagged and the PMON LCV Event Count Register (Address = 0x50 and 0x51) will also
be incremented. Additionally, the LCV-One-Second Accumulation Registers (Address = 0x6E and 0x6F) will
be incremented. For example: If the incoming E3 data is HDB3 encoded, the Receive E3 LIU Interface block
will also increment the LCV One-Second Accumulation Register if three (or more) consecutive zeros are re-
ceived.
6.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the RxPOS and the RxNEG input pins are clocked into the
Receive E3 LIU Interface block via the RxLineClk signal. The Framer IC allows the user to specify which edge
(e.g, rising or falling) of the RxLineClk signal will sample and latch the signal at the RxPOS and RxNEG input
signals into the Framer IC. The user can make this selection by writing the appropriate data to bit 1 of the I/O
Control Register, as depicted below.
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable
TxLOC
R/W
1
BIT 6
LOC
RO
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup
R/W
0
BIT 3
Unipolar/
Bipolar
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 81 depicts the relationship between the value of this bit-field to the sampling clock edge of RxLineClk.
TABLE 81: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL
REGISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL
RXLINECLK
(BIT 1)
RESULT
0 ^{Rising Edge:}
RxPOS and RxNEG are sampled at the rising edge of RxLineClk. See Figure 179 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
1 ^{Falling Edge:}
RxPOS and RxNEG are sampled at the falling edge of RxLineClk. See Figure 180 for timing relationship
between RxLineClk, RxPOS, and RxNEG.
Figure 179 and Figure 180 present the Waveform and Timing Relationships between RxLineClk, RxPOS and
RxNEG for each of these configurations.
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