XR72L52 Datasheet, PDF (161/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
2. Set the TimRefSel[1:0] bit-fields within the Framer Operating Mode Register to “00" as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loop-back DS3/E3
R/W
R/W
0
0
Internal LOS
Enable
R/W
1
RESET
R/W
0
Interrupt
Enable Reset
R/W
1
Frame Format
R/W
0
TimRefSel[1:0]
R/W
R/W
0
0
3. Interface the XRT72L52, to the Terminal Equipment, as illustrated in Figure 38.
The XRT72L52 cannot support the Framer Local Loop-back Mode of operation. The XRT72L52 Framer must
be configured into any of the following modes prior to configuring the Framer Local-Loop-back Mode operation.
• Mode 2 - Serial/Local-Timed/Frame-Slave Mode.
• Mode 3 - Serial/Local-Timed/Frame-Master Mode.
• Mode 5 - Nibble-Parallel/Local-Timed/Frame-Slave Mode.
• Mode 6 - Nibble-Parallel/Local-Timed/Frame-Master Mode.
NOTE: For more detailed information on the Framer Local Loop-back Mode Operation, please see Section 7.0.
4.2.1.5 Mode 5 - The Nibble-Parallel/Local-Timed/Frame-Slave Interface Mode Behavior of the
XRT72L52
The XRT72L52 configured to operate in this mode functions as follows:
Local-Timed
The Transmit Section of the XRT72L52 uses the TxInClk signal as its timing reference. The chip internally di-
vides the TxInClk clock signal by a factor of 4 and outputs this divided clock signal via the TxNibClk output pin.
The Transmit Terminal Equipment Input Interface block within the XRT72L52 uses the rising edge of the TxNib-
Clk signal to latch the data residing on the TxNib[3:0] into its circuitry.
Nibble-Parallel Mode
The XRT72L52 accepts the DS3 payload data from the Terminal Equipment in a parallel manner via the Tx-
Nib[3:0] input pins. The Transmit Terminal Equipment Input Interface latches this data into its circuitry on the
rising edge of the TxNibClk output signal.
Delineation of outbound DS3 Frames
The Transmit Section uses the TxInClk input signal as its timing reference and the TxFrameRef input signal as
its Framing Reference (e.g., the Transmit Section of the XRT72L52 initiates frame generation upon the rising
edge of the TxFrameRef signal).
In this case, the Terminal Equipment should pulse the TxFrameRef input signal of the XRT72L52 coincident
with it applying the first payload nibble within a given outbound DS3 frame. The duration of this pulse should
be one nibble-period of the DS3 signal (see Figure 41).
Sampling of payload data, from the Terminal Equipment
In Mode 5, the XRT72L52 samples the data at the TxNib[3:0] input pins on the third rising edge of the TxInClk
clock signal following a pulse in the TxNibClk signal (see Figure 41).
The TxNibClk signal from the XRT72L52 operates nominally at 11.184 MHz (e.g., 44.736 MHz divided by 4).
However, TxNibClk effectively operates at a Low clock frequency. The Transmit Payload Data Input Interface
is only used to accept the payload data which is intended to be carried by outbound DS3 frames. The Transmit
Payload Data Input Interface is not designed to accommodate the entire DS3 data stream.
The DS3 Frame consists of 4704 payload bits or 1176 nibbles. The XRT72L52 supplies 1176 TxNibClk pulses
between the rising edges of two consecutive TxNibFrame pulses. The DS3 Frame repetition rate is 9.398kHz.
1176 TxNibClk pulses for each DS3 frame period amounts to TxNibClk running at approximately 11.052 MHz.
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