XR72L52 Datasheet, PDF (276/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
Finally, the XRT72L52 will always internally generate the Overhead bits, when it is operating in both the E3 and
Nibble-parallel modes. The XRT72L52 will pull the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L52 and the Terminal Equipment for E3 Mode 6 Operation is il-
lustrated in Figure 99.
FIGURE 99. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 AND THE TERMINAL
EQUIPMENT (E3 MODE 6 OPERATION)
Terminal Equipment Signals
TxInClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [380]
Overhead Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [380]
Overhead Nibble [0]
TxOH_Ind
Note: TxNibFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 3 Nibble periods
How to configure the XRT72L52 into Mode 6
1. Set the NibIntfinput pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the Framer Operating Mode Register) to "1X" as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local
Loop-back
DS3/E3
R/W
R/W
0
0
Internal
LOS
Enable
R/W
1
RESET
R/W
0
Interrupt
Enable
Reset
R/W
1
Frame
Format
R/W
0
TimRefSel[1:0]
R/W
R/W
1
x
3. Interface the XRT72L52, to the Terminal Equipment, as illustrated in Figure 98.
5.2.2 The Transmit Overhead Data Input Interface
Figure 100 presents a simple illustration of the Transmit Overhead Data Input Interface block within the
XRT72L52.
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