XR72L52 Datasheet, PDF (348/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change in Receive LOS Condition Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do all of the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set Bit 1 (LOS Interrupt Status), within the Rx E3 Interrupt Status Register - 1 to “1”, as indicated below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COFA
OOF
LOF
LOS
AIS
Interrupt Status Interrupt Status Interrupt Status Interrupt Status Interrupt Status
RUR
RUR
RUR
RUR
RUR
0
0
0
1
0
Whenever the user’s system encounters the Change in Receive LOS Condition Interrupt, then it should do the
following.
1. It should determine the current state of the LOS condition. Recall, that this interrupt can be generated,
whenever the XRT72L52 Framer IC declares or clears the LOS defect. Hence, the user can determine the
current state of the LOS defect by reading the state of Bit 4 (RxLOS) within the Rx E3 Configuration and
Status Register - 2, as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
1
1
BIT 0
RxFERF
RO
1
If the LOS state is TRUE
1. It should transmit a FERF (Far-End-Receive Failure) indicator to the Remote Terminal Equipment. Please
see Section 5.2.4.2.1.3.
If the LOS state is FALSE
1. It should cease transmitting the FERF indication to the Remote Terminal Equipment.
NOTE: The device cannot be configured to automatically send/clear FERF on LOS, LOOf, OOF or AIS in E3 G.751 mode.
The user must implemt it in the ISR.
Please see Section 5.2.4.2.1.3 on how to control the state of the A bit, which is transmitted on each outbound
E3 frame.
5.3.6.2.2 The Change in Receive OOF Condition Interrupt
If the Change in Receive OOF Condition Interrupt is enabled, then the XRT72L52 Framer IC will generate an
interrupt in response to either of the following conditions.
1. When the XRT72L52 Framer IC declares an OOF (Out of Frame) Condition, and
2. When the XRT72L52 Framer IC clears the OOF condition.
Conditions causing the XRT72L52 Framer IC to declare an OOF Condition.
• If the Receive E3 Framer block (within the XRT72L52 Framer IC) detects Framing bit errors, within four con-
secutive incoming E3 frames.
Conditions causing the XRT72L52 Framer IC to clear the OOF Condition.
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