XR72L52 Datasheet, PDF (387/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
In this example, the Terminal Equipment intends to insert the appropriate overhead bits, into the Transmit
Overhead Data Input Interface, such that the XRT72L52 will transmit a Yellow Alarm to the remote terminal
equipment. Recall that, for E3 Applications, a Yellow Alarm is transmitted by setting the FERF bit (within the
MA Byte) to "0".
If one assumes that the connection between the Terminal Equipment and the XRT72L52 are as illustrated in
Figure 158 then Figure 159 presents an illustration of the signaling that must go on between the Terminal
Equipment and the XRT72L52.
FIGURE 159. ILLUSTRATION OF THE SIGNAL THAT MUST OCCUR BETWEEN THE TERMINAL EQUIPMENT AND THE
XRT72L52, IN ORDER TO CONFIGURE THE XRT72L52 TO TRANSMIT A YELLOW ALARM TO THE REMOTE TERMINAL
EQUIPMENT
Terminal Equipment/XRT72L5x Interface Signals
0
1
26
27
28
29
30
31
32
TxOHClk
TxOHFrame
TxOHIns
TxOH
Remaining Overhead Bits with E3 Frame
MA, Bit 7
TxOHFrame is sample “high”
Terminal Equipment asserts TxOHIns and
Data on TxOHline.
XRT72L5x Framer samples TxOHIns and
TxOHIns signal
In Figure 159 the Terminal Equipment samples the TxOHFrame signal being "High" at rising clock edge # “0".
From this point, the Terminal Equipment waits until it has detected 32 rising edges in the TxOHClk signal. At
this point, the Terminal Equipment knows that the XRT72L52 is just about to process the FERF bit within the
MA byte (in a given Outbound E3 frame). Additionally, according to Table 70, the 32nd overhead bit to be pro-
cessed is the FERF bit. In order to facilitate the transmission of the Yellow Alarm, the Terminal Equipment
must set this FERF bit to "1". Hence, the Terminal Equipment starts this process by implementing the following
steps concurrently.
a. Assert the TxOHIns input pin by setting it "High".
b. Set the TxOH input pin to "0".
After the Terminal Equipment has applied these signals, the XRT72L52 will sample the data on both the TxO-
HIns and TxOH signals upon the very next falling edge of TxOHClk (designated at 32- in Figure 159). Once
the XRT72L52 has sampled this data, it will then insert a "1" into the FERF bit position, in the Outbound E3
frame.
Upon detection of the very next rising edge of the TxOHClk clock signal (designated as clock edge 1 in
Figure 159), the Terminal Equipment will negate the TxOHIns signal (e.g., toggles it "Low") and will cease in-
serting data into the Transmit Overhead Data Input Interface.
6.2.2.2 Method 2 - Using the TxInClk and
TxOHEnable Signals
371