XR72L52 Datasheet, PDF (163/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 41. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 AND THE TERMINAL
EQUIPMENT (DS3 MODE 5 OPERATION)
Terminal Equipment Signals
TxInClk
DS3_Nib_Clock_In
DS3_Data_Out[3:0] Nibble [1175]
Tx_Start_of_Frame
Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
Nibble [1175]
TxFrameRef
Nibble [0]
DS3 Frame Number N
DS3 Frame Number N + 1
Note: TxFrameRef is pulsed high to denote
first nibble within a new DS3 frame
Nibble [1]
Nibble [1]
Sampling edge of the XRT72L5x
Device
How to configure the XRT72L52 into Mode 5
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields within the Framer Operating Mode Register to "01" as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loop-back DS3/E3 Internal LOS RESET
Enable
R/W
R/W
R/W
R/W
0
0
1
0
Interrupt
Enable Reset
R/W
1
Frame Format
R/W
0
TimRefSel[1:0]
R/W
R/W
0
1
3. Interface the XRT72L52, to the Terminal Equipment, as illustrated in Figure 40.
4.2.1.6 Mode 6 - The Nibble-Parallel/TxInClk/Frame-Master Interface Mode Behavior of the
XRT72L52
The XRT72L52 configured to operate in this mode, functions as follows:
Local-Timed
The Transmit Section of the XRT72L52 uses the TxInClk signal at its timing reference. The chip internally di-
vides the TxInClk clock signal by a factor of 4 and outputs this divided clock signal via the TxNibClk output pin.
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