XR72L52 Datasheet, PDF (469/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
• It should read the contents of the PMON Parity Error Event Count Registers (located at Addresses 0x54 and
0x55) in order to determine the number of BIP-8 Errors that have been received by the XRT72L52 Framer
IC.
6.3.6.2.10 The Detection of Framing Byte Error Interrupt
If the Detection of Framing Byte Error Interrupt is enabled, then the XRT72L52 Framer IC will generate an in-
terrupt, anytime the Receive E3 Framer block has received an E3 frame with an incorrect Framing Byte (e.g.,
FA1 or FA2) value.
Enabling and Disabling the Detection of Framing Byte Error Interrupt
The user can enable or disable the Detection of Framing Byte Error’ interrupt by writing the appropriate value
into Bit 1 (Framing Byte Error Interrupt Enable) within the Rx E3 Interrupt Enable Register - 2, as indicated be-
low.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
X
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Detection of Framing Byte Error Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int), by driving it "Low".
• It will set the Bit 1 (Framing Byte Error Interrupt Status), within the RxE3 Interrupt Status Register - 2 as indi-
cated below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Status
RUR
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Status
RUR
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-8
Error Interrupt
Status
RUR
0
BIT 1
Framing
Byte Error
Interrupt
Status
RUR
1
BIT 0
RxPld
Mis
Interrupt
Status
RUR
0
Whenever the Terminal Equipment encounters the Detection of Framing Byte Error Interrupt, it should do the
following.
• It should read the contents of the PMON Framing Bit/Byte Error Count Registers (located at Addresses 0x52
and 0x53) in order to determine the number of Framing Byte errors that have been received by the
XRT72L52 Framer IC.
6.3.6.2.11 The Detection of Payload Type Mismatch Interrupt
If the Detection of Payload Type Mismatch Interrupt is enabled, then the XRT72L52 Framer IC will generate an
interrupt, anytime the Receive E3 Framer block receives a MA byte (within an incoming E3 frame) that con-
tents a Payload Type value that is different from the expected Payload Type value.
Conditions causing this interrupt to be generated.
453