XR72L52 Datasheet, PDF (478/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
8.2.2.1 Receive Payload HDLC Processor
The receiver HDLC processor is the counter part of the transmit HDLC processor for formatting the payload
portion of the receive DS3/E3 data that is activated when the HDLCon bit in the HDLC Control register (0x82)
is set.
This receiver performs idle flag detection, stuffed zero removal, and FCS checking on the incoming data
stream. The recovered data bytes are presented on RxHDLCData[7:0] and are valid on the rising edge of Rx-
HDLCClk . The LSB is on RxHDLCData[0] and the MSB on RxHDLCData[7]; the LSB is the first received from
the serial input. User should sample RxHDLCData on falling edge of RxHDLCClk.
If the payload stream contains idle flags, the IDLE pin will be high and the flags will be present on RxHDLCDa-
ta[7:0]. If a valid FCS is received at the end of the message block, the ValidFCS pin will be active high while
RxIDLE is high. At the start of the next message, both indications will go low until the end of the incoming mes-
sage has been received. If a bad FCS is received, RxIDLE will go high and ValidFCS will remain low. If Valid-
FCS goes high and RxIDLE does not, an abort sequence was received in the data. If there is only one flag re-
ceived between incoming packets, there will be only one RxHDLCClk pulse present while RxIDLE is high. Tim-
ing for this operation is shown in Figure 205.
RxHDLCClk is generated from the receive DS3/E3 clock and is present continuously like the transmit byte
clock. Nominally there will be one pulse on RxHDLCClk for every eight clock cycles on the receive DS3/E3
clock. When an inserted transparency bit must be deleted or DS3/E3 overhead bits skipped, the clock period
will be stretched by one or more DS3/E3 clock cycles. RxHDLCClk is present during the reception of FCS oc-
tets and idle flags.
FIGURE 205. TIMING DIAGRAM FOR RXHDLC OPERATION
RxHDLCData[7:0]
Rx Idle
V alidF CS
Data Data
Data Flag
DataData Flag Data
Bad FCS
XX Flag
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