XR72L52 Datasheet, PDF (85/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Bit 3 - FERF Interrupt Status
This Reset Upon Read bit will be set to '1' if the Receive E3 Framer has detected a Change in the Rx FERF
Condition, since the last time this register was read.
This bit-field will be asserted under either of the following two conditions.
1. When the Receive DS3/E3 Framer block first detects the occurrence of an RxFERF Condition (e.g., when
the FERF bit, within the last 3 or 5 consecutive E3 frames are set to "1").
2. When the Receive DS3/E3 Framer block detects the end of the RxFERF Condition (e.g., when the FERF
bit, within the last 3 or 5 consecutive E3 frames are set to "0").
NOTE: For more information on the RxFERF (Yellow Alarm) condition, refer to Section 6.3.2.6.3.
Bit 2 - BIP-8 (EM Byte) Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the BIP-8 Error interrupt has occurred since the last read of
this register.
The Receive DS3/E3 Framer block will generate the BIP-8 Error interrupt if it has concluded that it has re-
ceived an errored E3 frame, from the Remote Terminal.
NOTE: Please see Section 6.3.6.2.9 for a more detailed discussion of this interrupt.
Bit 1 - Framing Byte Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Framing Byte Error interrupt has occurred since the last
read of this register.
The Receive DS3/E3 Framer block will generate the Framing Byte Error interrupt if it has detected an error in
the FA1 or FA2 bytes, on an incoming E3 frame.
NOTE: Please see Section 6.3.6.2.10 for a more detailed discussion of this interrupt.
Bit 0 - Rx Pld Mis Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Payload Type Mismatch interrupt has occurred since the
last read of this register.
The Receive DS3/E3 Framer block will generate the Payload Type Mismatch interrupt when it detects that the
values, within the Payload Type bit-fields of the incoming E3 frame, has changed from that of the previous E3
frame.
NOTE: Please see Section 6.3.6.2.11 for a more detailed discussion on this interrupt.
2.3.3.7 Receive E3 LAPD Control Register (E3, ITU-T G.832)
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
DL from NR
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
RO
RO
RO
R/W
R/W
R/W
RUR
0
0
0
0
0
0
0
0
Bit 3 - DL from NR
This Read/Write bit-field allows the user to specify whether the LAPD Receiver should retrieve the bytes, com-
prising the incoming LAPD Message frame, from the NR byte-field, or from the GC byte-field, within each in-
coming E3 frame.
Writing a "1" configures the LAPD Receiver to retrieve the incoming LAPD Message frame octets from the NR
byte-field, within each incoming E3 frame. Writing a "0" configures the LAPD Receiver to retrieve the incoming
LAPD Message frame octets from the GC byte.
Bit 2 - RxLAPD Enable
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